Datasheet

Data Sheet AD5122A/AD5142A
Rev. A | Page 13 of 32
1
2
3
4
5
6
7
8
INDEP
A1
W1
B1
RESET
A2
V
SS
GND
16
15
14
13
12
11
10
9
ADDR1
SDA
SCL
V
LOGIC
V
DD
W2
B2
AD5122A/
AD5142A
TOP VIEW
(Not to Scale)
ADDR0
10939-005
Figure 5. 16-Lead TSSOP Pin Configuration
Table 8. 16-Lead TSSOP Pin Function Descriptions
Pin No. Mnemonic Description
1 INDEP Linear Gain Setting Mode at Power-Up. Each string resistor is loaded from its associated memory location.
If INDEP is enabled, it cannot be disabled by the software.
2
RESET
Hardware Reset Pin. Refresh the RDAC registers from EEPROM.
RESET
is activated at logic low.
If this pin is not used, tie
RESET
to V
LOGIC
.
3 GND Ground Pin, Logic Ground Reference.
4 A1 Terminal A of RDAC1. V
SS
≤ V
A
≤ V
DD
.
5 W1 Wiper Terminal of RDAC1. V
SS
≤ V
W
≤ V
DD
.
6 B1 Terminal B of RDAC1. V
SS
≤ V
B
≤ V
DD
.
7 V
SS
Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
8 A2 Terminal A of RDAC2. V
SS
≤ V
A
≤ V
DD
.
9 W2 Wiper Terminal of RDAC2. V
SS
≤ V
W
≤ V
DD
.
10 B2 Terminal B of RDAC2. V
SS
≤ V
B
≤ V
DD
.
11 V
DD
Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
12 V
LOGIC
Logic Power Supply; 1.8 V to V
DD
. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
13 SCL Serial Clock Line.
14 SDA Serial Data Input/Output.
15
ADDR1
Programmable Address (ADDR1) for Multiple Package Decoding.
16 ADDR0 Programmable Address (ADDR0) for Multiple Package Decoding.