Datasheet

AD5122A/AD5142A Data Sheet
Rev. A | Page 12 of 32
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
RESET
ADDR0
NOTES
1. INTERNALLY CONNECT THE
EXPOSED PAD TO V
SS
.
AD5122A/
AD5142A
TOP VIEW
(Not to Scale)
PIN 1
INDIC
A
T
OR
1GND
2
A1
3
W1
4B1
1
1
SC
L
12
SDA
10
V
LOGIC
9 V
DD
INDE
P
ADDR1
5
V
SS
6
A2
7
W2
8
B2
15
16
14
13
10939-004
Figure 4. 16-Lead LFCSP Pin Configuration
Table 7. 16-Lead LFCSP Pin Function Descriptions
Pin No. Mnemonic Description
1 GND Ground Pin, Logic Ground Reference.
2 A1 Terminal A of RDAC1. V
SS
≤ V
A
≤ V
DD
.
3 W1 Wiper Terminal of RDAC1. V
SS
≤ V
W
≤ V
DD
.
4 B1 Terminal B of RDAC1. V
SS
≤ V
B
≤ V
DD
.
5 V
SS
Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
6 A2 Terminal A of RDAC2. V
SS
≤ V
A
≤ V
DD
.
7 W2 Wiper Terminal of RDAC2. V
SS
≤ V
W
≤ V
DD
.
8 B2 Terminal B of RDAC2. V
SS
≤ V
B
≤ V
DD
.
9
V
DD
Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
10 V
LOGIC
Logic Power Supply; 1.8 V to V
DD
. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
11 SCL Serial Clock Line.
12 SDA Serial Data Input/Output.
13 ADDR1 Programmable Address (ADDR1) for Multiple Package Decoding.
14
ADDR0
Programmable Address (ADDR0) for Multiple Package Decoding.
15 INDEP Linear Gain Setting Mode at Power-Up. Each string resistor is loaded from its associated memory location.
If INDEP is enabled, it cannot be disabled by the software.
16
RESET
Hardware Reset Pin. Refresh the RDAC registers from EEPROM.
RESET
is activated at logic low.
If this pin is not used, tie
RESET
to V
LOGIC
.
EPAD Internally Connect the Exposed Pad to V
SS
.