Datasheet

Data Sheet AD5124/AD5144/AD5144A
Rev. A | Page 31 of 36
RDAC ARCHITECTURE
To achieve optimum performance, Analog Devices, Inc., has
patented the RDAC segmentation architecture for all the digital
potentiometers. In particular, the AD5124/AD5144 employ a
three-stage segmentation approach, as shown in Figure 45. The
AD5124/AD5144/AD5144A wiper switch is designed with the
transmission gate CMOS topology and with the gate voltage
derived from V
DD
and V
SS
.
7-BIT/8-BIT
ADDRESS
DECODER
R
L
W
R
L
A
R
H
R
H
R
M
R
M
B
R
M
R
M
R
H
R
H
S
TS
S
BS
10877-048
Figure 45. AD5124/AD5144/AD5144A Simplified RDAC Circuit
Top Scale/Bottom Scale Architecture
In addition, the AD5124/AD5144/AD5144A include new
positions to reduce the resistance between terminals. These
positions are called bottom scale and top scale. At bottom scale,
the typical wiper resistance decreases from 130 Ω to 60 Ω (R
AB
=
100 kΩ). At top scale, the resistance between Terminal A and
Terminal W is decreased by 1 LSB, and the total resistance is
reduced to 60 Ω (R
AB
= 100 kΩ).
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation—±8% Resistor Tolerance
The AD5124/AD5144/AD5144A operate in rheostat mode when
only two terminals are used as a variable resistor. The unused
terminal can be floating, or it can be tied to Terminal W, as shown
in Figure 46.
A
W
B
A
W
B
A
W
B
10877-049
Figure 46. Rheostat Mode Configuration
The nominal resistance between Terminal A and Terminal B,
R
AB
, is 10 k or 100 k, and has 128/256 tap points accessed by
the wiper terminal. The 7-bit/8-bit data in the RDAC latch is
decoded to select one of the 128/256 possible wiper settings. The
general equations for determining the digitally programmed
output resistance between Terminal W and Terminal B are
AD5124:
W
AB
WB
RR
D
DR 
128
)(
From 0x00 to 0x7F (1)
AD5144/AD5144A:
W
AB
WB
RR
D
DR 
256
)(
From 0x00 to 0xFF (2)
where:
D is the decimal equivalent of the binary code in the 7-bit/8-bit
RDAC register.
R
AB
is the end-to-end resistance.
R
W
is the wiper resistance.
In potentiometer mode, similar to the mechanical potentiometer,
the resistance between Terminal W and Terminal A also produces
a digitally controlled complementary resistance, R
WA
. R
WA
also
gives a maximum of 8% absolute resistance error. R
WA
starts at the
maximum resistance value and decreases as the data loaded into
the latch increases. The general equations for this operation are
AD5124:
W
ABAW
RR
D
DR 


128
128
)(
From 0x00 to 0x7F (3)
AD5144/AD5144A:
W
ABAW
RR
D
DR 


256
256
)(
From 0x00 to 0xFF (4)
where:
D is the decimal equivalent of the binary code in the 7-bit/8-bit
RDAC register.
R
AB
is the end-to-end resistance.
R
W
is the wiper resistance.