Datasheet

AD5124/AD5144/AD5144A Data Sheet
Rev. A | Page 30 of 36
Table 21. Address Bits
A3 A2 A1 A0
Potentiometer Mode Linear Gain Setting Mode
Stored RDAC
Memory Input Register RDAC Register Input Register RDAC Register
1 X
1
X
1
X
1
All channels All channels All channels All channels Not applicable
0 0 0 0 RDAC1 RDAC1 R
WB1
R
WB1
RDAC1
0 1 0 0 Not applicable Not applicable R
AW1
R
AW1
Not applicable
0 0 0 1 RDAC2 RDAC2 R
WB2
R
WB2
RDAC2
0 1 0 1 Not applicable Not applicable R
AW2
R
AW2
Not applicable
0 0 1 0 RDAC3 RDAC3 R
WB3
R
WB3
RDAC3
0 1 1 0 Not applicable Not applicable R
AW3
R
AW3
Not applicable
0 0 1 1 RDAC4 RDAC4 R
WB4
R
WB4
RDAC4
0 1 1 1 Not applicable Not applicable R
AW4
R
AW4
Not applicable
1
X = don’t care.
Table 22. Control Register Bit Descriptions
Bit Name Description
D0 RDAC register write protect
0 = wiper position frozen to value in EEPROM memory
1 = allows update of wiper position through digital interface (default)
D1 EEPROM program enable
0 = EEPROM program disabled
1 = enables device for EEPROM program (default)
D2 Linear setting mode/potentiometer mode
0 = potentiometer mode (default)
1 = linear gain setting mode
D3 Burst mode (I
2
C only)
0 = disabled (default)
1 = enabled (no disable after stop or repeat start condition)