Datasheet

Data Sheet AD5124/AD5144/AD5144A
Rev. A | Page 15 of 36
1
2
3
4
5
6
7
8
9
10
GND
A1
W1
W3
A3
B1
RESET
A2
V
SS
B3
20
19
18
17
16
15
14
13
12
11
SDA
SCL
V
LOGIC
W4
B4
V
DD
W2
B2
A4
ADDR
AD5144A
TOP VIEW
(Not to Scale)
10877-011
Figure 10. 20-Lead TSSOP, I
2
C Interface Pin Configuration (AD5144A)
Table 10. 20-Lead TSSOP, I
2
C Interface Pin Function Descriptions (AD5144A)
Pin No. Mnemonic Description
1
RESET
Hardware Reset Pin. Refresh the RDAC registers from EEPROM.
RESET
is activated at the logic low. If this pin is not
used, tie
RESET
to V
LOGIC
.
2 GND Ground Pin, Logic Ground Reference.
3 A1 Terminal A of RDAC1. V
SS
≤ V
A
≤ V
DD
.
4 W1 Wiper Terminal of RDAC1. V
SS
≤ V
W
≤ V
DD
.
5 B1 Terminal B of RDAC1. V
SS
≤ V
B
≤ V
DD
.
6 A3 Terminal A of RDAC3. V
SS
≤ V
A
≤ V
DD
.
7 W3 Wiper Terminal of RDAC3. V
SS
≤ V
W
≤ V
DD
.
8 B3 Terminal B of RDAC3. V
SS
≤ V
B
≤ V
DD
.
9
V
SS
Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
10 A2 Terminal A of RDAC2. V
SS
≤ V
A
≤ V
DD
.
11 W2 Wiper Terminal of RDAC2. V
SS
≤ V
W
≤ V
DD
.
12 B2 Terminal B of RDAC2. V
SS
≤ V
B
≤ V
DD
.
13 A4 Terminal A of RDAC4. V
SS
≤ V
A
≤ V
DD
.
14 W4 Wiper Terminal of RDAC4. V
SS
≤ V
W
≤ V
DD
.
15 B4 Terminal B of RDAC4. V
SS
≤ V
B
≤ V
DD
.
16 V
DD
Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
17 V
LOGIC
Logic Power Supply; 1.8 V to V
DD
. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
18 SCL Serial Clock Line. Data is clocked in at the logic low transition.
19 SDA Serial Data Input/Output.
20 ADDR Programmable Address for Multiple Package Decoding.