Datasheet

AD5124/AD5144/AD5144A Data Sheet
Rev. A | Page 14 of 36
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
GND
A1
W1
W3
A3
B1
SYNC
A2
V
SS
B3
20
19
18
17
16
15
14
13
12
11
SDI
SCLK
V
LOGIC
W4
B4
V
DD
W2
B2
A4
SDO
AD5124/
AD5144
TOP VIEW
(Not to Scale)
10877-010
Figure 9. 20-Lead TSSOP, SPI Interface Pin Configuration (AD5124/AD5144)
Table 9. 20-Lead TSSOP, SPI Interface Pin Function Descriptions (AD5124/AD5144)
Pin No. Mnemonic Description
1
SYNC
Synchronization Data Input, Active Low. When
SYNC
returns high, data is loaded into the input shift register.
2 GND Ground Pin, Logic Ground Reference.
3 A1 Terminal A of RDAC1. V
SS
≤ V
A
≤ V
DD
.
4 W1 Wiper Terminal of RDAC1. V
SS
≤ V
W
≤ V
DD
.
5 B1 Terminal B of RDAC1. V
SS
≤ V
B
≤ V
DD
.
6 A3 Terminal A of RDAC3. V
SS
≤ V
A
≤ V
DD
.
7 W3 Wiper Terminal of RDAC3. V
SS
≤ V
W
≤ V
DD
.
8 B3 Terminal B of RDAC3. V
SS
≤ V
B
≤ V
DD
.
9 V
SS
Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
10 A2 Terminal A of RDAC2. V
SS
≤ V
A
≤ V
DD
.
11 W2 Wiper Terminal of RDAC2. V
SS
≤ V
W
≤ V
DD
.
12
B2
Terminal B of RDAC2. V
SS
≤ V
B
≤ V
DD
.
13 A4 Terminal A of RDAC4. V
SS
≤ V
A
≤ V
DD
.
14 W4 Wiper Terminal of RDAC4. V
SS
≤ V
W
≤ V
DD
.
15 B4 Terminal B of RDAC4. V
SS
≤ V
B
≤ V
DD
.
16 V
DD
Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
17 V
LOGIC
Logic Power Supply; 1.8 V to V
DD
. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
18 SCLK Serial Clock Line. Data is clocked in at the logic low transition.
19 SDI Serial Data Input.
20 SDO Serial Data Output. This is an open-drain output pin, and it needs an external pull-up resistor.