Datasheet

AD5124/AD5144/AD5144A Data Sheet
Rev. A | Page 16 of 36
10877-009
PIN 1
INDICATOR
1
GND
2
A1
3
W1
4B1
5
A3
6W3
15
V
DD
16 V
LOGIC
17 SCL/SCLK
NOTES
1. INTERNALLY CONNECT THE
EXPOSED PAD TO V
SS
.
18
DIS
14 B4
13
W4
7
B3
8
V
SS
9
A2
1
1
B2
12
A4
10
W2
21
ADDR1/SDO
22
ADDR0/SYNC
23
LRDAC
24
RESET
20
W
P
19
SDA/SDI
AD5124/
AD5144
TOP VIEW
(Not to Scale)
Figure 11. 24-Lead LFCSP Pin Configuration (AD5124/AD5144)
Table 11. 24-Lead LFCSP Pin Function Descriptions (AD5124/AD5144)
Pin No. Mnemonic Description
1 GND Ground Pin, Logic Ground Reference.
2 A1 Terminal A of RDAC1. V
SS
≤ V
A
≤ V
DD
.
3 W1 Wiper Terminal of RDAC1. V
SS
≤ V
W
≤ V
DD
.
4 B1 Terminal B of RDAC1. V
SS
≤ V
B
≤ V
DD
.
5 A3 Terminal A of RDAC3. V
SS
≤ V
A
≤ V
DD
.
6 W3 Wiper Terminal of RDAC3. V
SS
≤ V
W
≤ V
DD
.
7 B3 Terminal B of RDAC3. V
SS
≤ V
B
≤ V
DD
.
8 V
SS
Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
9 A2 Terminal A of RDAC2. V
SS
≤ V
A
≤ V
DD
.
10 W2 Wiper Terminal of RDAC2. V
SS
≤ V
W
≤ V
DD
.
11 B2 Terminal B of RDAC2. V
SS
≤ V
B
≤ V
DD
.
12 A4 Terminal A of RDAC4. V
SS
≤ V
A
≤ V
DD
.
13 W4 Wiper Terminal of RDAC4. V
SS
≤ V
W
≤ V
DD
.
14 B4 Terminal B of RDAC4. V
SS
≤ V
B
≤ V
DD
.
15 V
DD
Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
16 V
LOGIC
Logic Power Supply; 1.8 V to V
DD
. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
17
SCL/SCLK
I
2
C Serial Clock Line (SCL). Data is clocked in at the logic low transition.
SPI Serial Clock Line (SCLK). Data is clocked in at the logic low transition.
18 DIS Digital Interface Select (SPI/I
2
C Select). SPI when DIS = 0 (GND), and I
2
C when DIS = 1 (V
LOGIC
). This pin cannot be
left floating.
19 SDA/SDI Serial Data Input/Output (SDA), When DIS = 1.
Serial Data Input (SDI), When DIS = 0.
20
WP
Optional Write Protect. This pin prevents any changes to the present RDAC and EEPROM content, except when
reloading the content of the EEPROM into the RDAC register.
WP
is activated at logic low. If this pin is not used,
tie
WP
to V
LOGIC
.
21 ADDR1/SDO Programmable Address (ADDR1) for Multiple Package Decoding, When DIS = 1.
Serial Data Output (SDO). Open-drain output, needs an external pull-up resistor, when DIS = 0.
22 ADDR0/
SYNC
Programmable Address (ADDR0) for Multiple Package Decoding, When DIS = 1.
Synchronization Data Input, When DIS = 0. This pin is active low. When
SYNC
returns high, data is loaded into
the input shift register.
23
LRDAC
Load RDAC. Transfers the contents of the input registers to their respective RDAC registers when their
associated input registers were previously loaded using Command 2 (see Table 20). This allows simultaneous
update of all RDAC registers.
LRDAC
is activated at the high-to-low transition. If not used, tie
LRDAC
to V
LOGIC
.
24
RESET
Hardware Reset Pin. Refresh the RDAC registers from EEPROM.
RESET
is activated at the logic low. If not used,
tie
RESET
to V
LOGIC
.
EPAD Internally Connect the Exposed Pad to V
SS
.