Datasheet

Data Sheet AD5121/AD5141
Rev. A | Page 29 of 32
TERMINAL VOLTAGE OPERATING RANGE
The AD5121/AD5141 are designed with internal ESD diodes
for protection. These diodes also set the voltage boundary of
the terminal operating voltages. Positive signals present on
Terminal A, Terminal B, or Terminal W that exceed V
DD
are
clamped by the forward-biased diode. There is no polarity
constraint between V
A
, V
W
, and V
B
, but they cannot be higher
than V
DD
or lower than V
SS
.
V
DD
A
W
B
V
SS
10940-051
Figure 44. Maximum Terminal Voltages Set by V
DD
and V
SS
POWER-UP SEQUENCE
Because there are diodes to limit the voltage compliance at
Terminal A, Terminal B, and Terminal W (see Figure 44), it is
important to power up V
DD
first before applying any voltage to
Terminal A, Terminal B, and Terminal W. Otherwise, the diode
is forward-biased such that V
DD
is powered unintentionally. The
ideal power-up sequence is V
SS
, V
DD
, V
LOGIC
, digital inputs, and
V
A
, V
B
, and V
W
. The order of powering V
A
, V
B
, V
W
, and digital
inputs is not important as long as they are powered after V
SS
,
V
DD
, and V
LOGIC
. Regardless of the power-up sequence and the
ramp rates of the power supplies, once V
LOGIC
is powered, the
power-on preset activates, which restores EEPROM values to
the RDAC registers.
LAYOUT AND POWER SUPPLY BIASING
It is always a good practice to use a compact, minimum lead
length layout design. Ensure that the leads to the input are as
direct as possible with a minimum conductor length. Ground
paths should have low resistance and low inductance. It is also
good practice to bypass the power supplies with quality capacitors.
Apply low equivalent series resistance (ESR) 1 μF to 10 μF
tantalum or electrolytic capacitors at the supplies to minimize
any transient disturbance and to filter low frequency ripple.
Figure 45 illustrates the basic supply bypassing configuration
for the AD5121/AD5141.
AD5121/
AD5141
10940-052
V
DD
V
LOGIC
V
DD
+
V
DD
C1
0.1µF
C3
10µF
+
C2
0.1µF
C4
10µF
V
SS
V
LOGIC
+
C5
0.1µF
C6
10µF
GND
Figure 45. Power Supply Bypassing