Datasheet

AD5121/AD5141 Data Sheet
Rev. A | Page 24 of 32
Incrementing the wiper position by +6 dB essentially doubles
the RDAC register value, whereas decrementing the wiper
position by −6 dB halves the register content. Internally, the
AD5121/AD5141 use shift registers to shift the bits left and
right to achieve a ±6 dB increment or decrement. These functions
are useful for various audio/video level adjustments, especially
for white LED brightness settings in which human visual responses
are more sensitive to large adjustments than to small adjustments.
Table 14. Detailed Left Shift and Right Shift Functions for
the ±6 dB Step Increment and Decrement
Left Shift (+6 dB/Step) Right Shift (−6 dB/Step)
0000 0000 1111 1111
0000 0001 0111 1111
0000 0010 0011 1111
0000 0100 0001 1111
0000 1000 0000 1111
0001 0000 0000 0111
0010 0000 0000 0011
0100 0000 0000 0001
1000 0000 0000 0000
1111 1111 0000 0000
Burst Mode (I
2
C Only)
By enabling the burst mode, multiple data bytes can be sent to the
part consecutively. After the command byte, the part interprets the
consecutive bytes as data bytes for the first command.
A new command can be sent by generating a repeat start or by a
stop and start condition.
The burst mode is activated by setting Bit D3 of the control
register (see Table 18), and if a reset or power-down is performed,
it automatically resets.
Reset
The AD5121/AD5141 can be reset through software by
executing Command 14 (see Table 16) or through hardware on
the low pulse of the
RESET
pin. The reset command loads the
RDAC register with the contents of the EEPROM and takes
approximately 30 µs. The EEPROM is preloaded to midscale at
the factory, and initial power-up is, accordingly, at midscale.
Tie
RESET
to V
DD
if the
RESET
pin is not used.
Shutdown Mode
The AD5121/AD5141 can be placed in shutdown mode by
executing the software shutdown command, Command 15 (see
Table 16); and by setting the LSB (D0) to 1. This feature places
the RDAC in a special state. The contents of the RDAC register are
unchanged by entering shutdown mode. However, all commands
listed in Table 16 are supported while in shutdown mode. Execute
Command 15 (see Table 16) and set the LSB (D0) to 0 to exit
shutdown mode.
Table 15. Truth Table for Shutdown Mode
Linear Gain Setting Mode Potentiometer Mode
A2 AW WB AW WB
0 N/A
1
Open Open R
BS
1 Open N/A
1
N/A
1
N/A
1
1
N/A = not applicable.
EEPROM OR RDAC REGISTER PROTECTION
The EEPROM and RDAC registers can be protected by disabling
any update to these registers. This can be done by using software or
by using hardware. If these registers are protected by software,
set Bit D0 and/or Bit D1 (see Table 18), which protects the RDAC
and EEPROM registers independently.
If the registers are protected by hardware, pull the
WP
pin low.
If the
WP
pin is pulled low when the part is executing a command,
the protection is not enabled until the command is completed.
When RDAC is protected, the only operation allowed is to copy
the EEPROM into the RDAC register.
LOAD RDAC INPUT REGISTER (
LRDAC
)
LRDAC
software or hardware transfers data from the input
register to the RDAC register (and therefore updates the wiper
position). By default, the input register has the same value as the
RDAC register; therefore, only the input register that has been
updated using Command 2 is updated.
Software
LRDAC
, Command 8, allows updating of a single RDAC
register or all of the channels at once (see Table 16). This is a
synchronous update.
The hardware
LRDAC
is completely asynchronous and copies
the content of all the input registers into the associated RDAC
registers. If a command is executed, to avoid data corruption,
any transition in the
LRDAC
pin is ignored by the part.
INDEP PIN
If the INDEP pin is pulled high at power-up, the part operates
in linear gain setting mode, loading each string resistor, R
AW
and
R
WB
, with the value stored into the EEPROM (see Table 17). If
the pin is pulled low, the part powers up in potentiometer mode.
The INDEP pin and the D2 bit are connected internally to a logic
OR gate, if any or both are 1, the part cannot operate in
potentiometer mode (see Table 18).