Datasheet

AD5121/AD5141 Data Sheet
Rev. A | Page 22 of 32
I
2
C SERIAL DATA INTERFACE
The AD5141 has 2-wire, I
2
C-compatible serial interface. These
devices can be connected to an I
2
C bus as a slave device, under the
control of a master device. See Figure 3 for a timing diagram of a
typical write sequence.
The AD5141 supports standard (100 kHz) and fast (400 kHz) data
transfer modes. Support is not provided for 10-bit addressing
and general call addressing.
The 2-wire serial bus protocol operates as follows:
1. The master initiates a data transfer by establishing a start
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high. The following byte is
the address byte, which consists of the 7-bit slave address
and an R/
W
bit. The slave device corresponding to the
transmitted address responds by pulling SDA low during
the ninth clock pulse (this is called the acknowledge bit).
At this stage, all other devices on the bus remain idle while
the selected device waits for data to be written to, or read
from, its shift register.
If the R/
W
bit is set high, the master reads from the slave
device. However, if the R/
W
bit is set low, the master writes
to the slave device.
2. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge bit).
The transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of SCL.
3. When all data bits have been read from or written to, a stop
condition is established. In write mode, the master pulls the
SDA line high during the tenth clock pulse to establish a stop
condition. In read mode, the master issues a no acknowledge
for the ninth clock pulse (that is, the SDA line remains high).
The master then brings the SDA line low before the tenth
clock pulse, and then high again during the tenth clock pulse
to establish a stop condition.
I
2
C ADDRESS
The AD5141 has two different pin address options available, as
shown in Table 10.
Table 10. 24-Lead LFCSP Device Address Selection
ADDR0 Pin ADDR1 Pin 7-Bit I
2
C Device Address
V
LOGIC
V
LOGIC
0100000
No connect
1
V
LOGIC
0100010
GND V
LOGIC
0100011
V
LOGIC
No connect
1
0101000
No connect
1
No connect
1
0101010
GND No connect
1
0101011
V
LOGIC
GND 0101100
No connect
1
GND 0101110
GND GND 0101111
1
Not available in bipolar mode (V
SS
< 0 V) or in low voltage mode (V
LOGIC
= 1.8 V).
Table 11. Simple Command Operation Truth Table
Command
Number
Control
Bits[DB15:DB12]
Address
Bits[DB11:DB8]
1
Data Bits[DB7:DB0]
1
C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation
0 0 0 0 0 X X X X X X X X X X X X NOP: do nothing
1 0 0 0 1 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial register
data to RDAC
2 0 0 1 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial register
data to input register
3 0 0 1 1 X 0 0 0 X X X X X X D1 D0 Read back contents
D1 D0 Data
0 1 EEPROM
1 1 RDAC
9 0 1 1 1 X X 0 0 X X X X X X X 1 Copy RDAC register to EEPROM
10 0 1 1 1 X X 0 0 X X X X X X X 0 Copy EEPROM into RDAC
14 1 0 1 1 X X X X X X X X X X X X Software reset
15 1 1 0 0 0 0 0 0 X X X X X X X D0 Software shutdown
D0 Condition
0 Normal mode
1 Shutdown mode
1
X = don’t care.