Datasheet

Data Sheet AD5121/AD5141
Rev. A | Page 13 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDIC
A
TOR
1
GND
2A
3W
4B
V
DD
V
SS
11
V
LOGIC
SCLK/SC
L
NOTES
1. INTERNALLY CONNECT THE
EXPOSED PAD TO V
SS
.
12
SDI/SD
A
10
9
5
6
7
8
DIS
14
SDO/ADDR1
16
INDE
P
15
LRDAC
W
P
13
AD5121/
AD5141
TO
P
VIEW
(Not to Scale)
RESET
SYNC/ADDR0
10940-009
Figure 7. Pin Configuration
Table 9. Pin Function Descriptions
Pin No. Mnemonic Description
1 GND Ground Pin, Logic Ground Reference.
2 A Terminal A of RDAC. V
SS
≤ V
A
≤ V
DD
.
3 W Wiper terminal of RDAC. V
SS
≤ V
W
≤ V
DD
.
4 B Terminal B of RDAC. V
SS
≤ V
B
≤ V
DD
.
5 V
SS
Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
6
SYNC
/ADDR0 Programmable Address (ADDR0) for Multiple Package Decoding, DIS = 1.
Synchronization Data Input, Active Low. When
SYNC
returns high, data is loaded into the RDAC register, DIS = 0.
7
RESET
Hardware Reset Pin. Refresh the RDAC registers from EEPROM.
RESET
is activated at logic low. If this pin is not
used, tie
RESET
to V
LOGIC
.
8 DIS Digital Interface Select (SPI/I
2
C Select). SPI when DIS = 0 (GND), I
2
C when DIS = 1 (V
LOGIC
). This pin cannot be left
floating.
9 V
DD
Positive Power Supply. Decouple this pin with 0.1µF ceramic capacitors and 10 µF capacitors.
10 V
LOGIC
Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
11 SCLK/SCL SPI Serial Clock Line (SCLK). Data is clocked in at logic low transition.
I
2
C Serial Clock Line (SCL). Data is clocked in at logic low transition.
12 SDI/SDA Serial Data Input/Output (SDA), When DIS = 1.
Serial Data Input (SDI), When DIS = 0.
13
WP
Optional Write Protect. This pin prevents any changes to the present RDAC and EEPROM contents, except when
reloading the content of the EEPROM into the RDAC register.
WP
is activated at logic low. If this pin is not used,
tie
WP
to V
LOGIC
14 SDO/ADDR1 Programmable Address (ADDR1) for Multiple Package Decoding, When DIS = 1.
Serial Data Output (SDO). This is an open-drain output pin, and it needs an external pull-up resistor when DIS = 0.
15 INDEP Linear Gain Setting Mode at Power-Up. Each string resistor is loaded from its associate memory location. If
INDEP is enabled, it cannot be disabled by the software.
16
LRDAC
Load RDAC. Transfers the contents of the input register to the RDAC register. This allows asynchronous RDAC
update.
LRDAC
is activated low. If this pin is not used, tie
LRDAC
to V
LOGIC
.
EPAD Internally Connect the Exposed Pad to V
SS
.