Datasheet

Data Sheet AD5121/AD5141
Rev. A | Page 11 of 32
C3
t
4
t
2
t
3
t
5
t
6
C2 C1 C0 D7 D6 D5 D2 D1 D0
SDI
*
PREVIOUS COMMAND RECEIVED.
SCLK
SYNC
C3*
SDO
C2* C1* C0* D7* D6* D5* D2* D1* D0*
t
8
t
9
t
10
t
7
t
1
10940-007
Figure 5. SPI Serial Interface Timing Diagram, CPOL = 1, CPHA = 0
SPI INTERFACE
I
2
C INTERFACE
SCL
SCLK
SYNC
SDA
LRDAC
RESET
P
t
1
t
2
t
3
10940-008
Figure 6. Control Pins Timing Diagram