Datasheet

AD5121/AD5141 Data Sheet
Rev. A | Page 10 of 32
Parameter
1
Test Conditions/Comments Min Typ Max Unit Description
t
12
Standard mode 300 ns Fall time of SCL signal, t
FCL
Fast mode 20 + 0.1 C
L
300 ns
t
SP
3
Fast mode 0 50 ns Pulse width of suppressed spike (not shown in Figure 3)
1
Maximum bus capacitance is limited to 400 pF.
2
The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate; however, it has a negative effect on the
EMC behavior of the part.
3
Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode.
Table 6. Control Pins
Parameter Min Typ Max Unit Description
t
1
1 μs
End command to LRDAC falling edge
t
2
50 ns
Minimum LRDAC low time
t
3
0.1 10 μs
RESET low time
t
EEPROM_PROGRAM
1
15 50 ms Memory program time (not shown in Figure 6)
t
EEPROM_READBACK
7 30 μs Memory readback time (not shown in Figure 6)
t
POWER_UP
2
75 μs Power-on EEPROM restore time (not shown in Figure 6)
t
RESET
30 μs Reset EEPROM restore time (not shown in Figure 6)
1
EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at lower temperatures and higher write cycles.
2
Maximum time after V
DD
− V
SS
is equal to 2.3 V.
SHIFT REGISTER AND TIMING DIAGRAMS
DATA BITS
DB8DB15 (MSB) DB0 (LSB)
D7 D6 D5 D4 D3
D2 D1
D0
ADDRESS BITS
A0A1
A2C2 C1 C0 A3C3
CONTROL BITS
DB7
10940-004
Figure 2. Input Shift Register Contents
t
7
t
6
t
2
t
4
t
11
t
12
t
6
t
5
t
10
t
1
SCL
SD
A
PS S P
t
3
t
8
t
9
10940-005
Figure 3. I
2
C Serial Interface Timing Diagram (Typical Write Sequence)
C3
t
4
t
2
t
3
t
5
t
6
C2 C1 C0 D7 D6 D5 D2 D1 D0SDI
*PREVIOUS COMMAND RECEIVED.
SCLK
SYNC
C3*SDO C2* C1* C0* D7* D6* D5* D2* D1* D0*
t
8
t
9
t
10
t
7
t
1
10940-006
Figure 4. SPI Serial Interface Timing Diagram, CPOL = 0, CPHA = 1