Datasheet
Data Sheet AD5110/AD5112/AD5114
Rev. B | Page 9 of 28
INTERFACE TIMING SPECIFICATIONS
V
LOGIC
= 1.8 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 5.
Parameter
1
Test Conditions/
Comments
Min Typ Max Unit Description
f
SCL
2
Standard mode 100 kHz Serial clock frequency
Fast mode 400 kHz
t
1
Standard mode 4.0 µs t
HIGH
, SCL high time
Fast mode
0.6
µs
t
2
Standard mode 4.7 µs t
LOW
, SCL low time
Fast mode 1.3 µs
t
3
Standard mode 250 ns t
SU ;DAT
, data setup time
Fast mode 100 ns
t
4
Standard mode 0 3.45 µs t
HD ; DAT
, data hold time
Fast mode 0 0.9 µs
t
5
Standard mode 4.7 µs t
SU;STA
, setup time for a repeated start condition
Fast mode 0.6 µs
t
6
Standard mode 4 µs t
HD;STA
, hold time (repeated) start condition
Fast mode 0.6 µs
t
7
Standard mode 4.7 µs t
BUF
, bus free time between a stop and a start
condition
Fast mode 1.3 µs
t
8
Standard mode 4 µs t
SU;STO
, setup time for stop condition
Fast mode 0.6 µs
t
9
Standard mode 1000 ns t
RDA
, rise time of SDA signal
Fast mode
20 + 0.1 C
L
300
ns
t
10
Standard mode 300 ns t
FDA
, fall time of SDA signal
Fast mode 20 + 0.1 C
L
300 ns
t
11
Standard mode 1000 ns t
RCL
, rise time of SCL signal
Fast mode 20 + 0.1 C
L
300 ns
t
11A
Standard mode 1000 ns t
RCL1
, rise time of SCL signal after a repeated start
condition and after an acknowledge bit.
Fast mode 20 + 0.1 C
L
300 ns
t
12
Standard mode 300 ns t
FCL
, fall time of SCL signal
Fast mode 20 + 0.1 C
L
300 ns
t
SP
3
Fast mode 0 50 ns Pulse width of suppressed spike
t
EEPROM_PROGRAM
4
15 50 ms Memory program time
t
POWER_UP
5
50 µs Power-on EEPROM restore time
t
RESET
25
µs
Reset EEPROM restore time
1
Maximum bus capacitance is limited to 400 pF.
2
The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior
of the part.
3
Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 50 ns for fast mode.
4
EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at a lower temperature and higher write cycles.
5
Maximum time after V
DD
is equal to 2.3 V.