Datasheet
AD5110/AD5112/AD5114 Data Sheet
Rev. B | Page 6 of 28
Parameter Symbol Test Conditions/Comments Min Typ
1
Max Unit
POWER SUPPLIES
Single-Supply Power Range 2.3 5.5 V
Logic Supply Range 1.8 V
DD
V
Positive Supply Current I
DD
V
DD
= 5 V 0.75 3.5 µA
V
DD
= 2.7 V 2.5 µA
V
DD
= 2.3 V 2.4 µA
EEMEM Store Current
3
, 6
I
DD_NVM_STORE
2 mA
EEMEM Read Current
3, 7
I
DD_NVM_READ
320 µA
Logic Supply Current I
LOGIC
V
IH
= V
LOGIC
or V
IL
= GND 30 nA
Power Dissipation
8
P
DISS
V
IH
= V
LOGIC
or V
IL
= GND 5 µW
Power Supply Rejection
3
PSR ∆V
DD
/∆V
SS
= 5 V ± 10%
R
AB
= 5 kΩ −43 dB
R
AB
=10 kΩ −50 dB
R
AB
= 80 kΩ −64 dB
DYNAMIC CHARACTERISTICS
3
, 9
Bandwidth BW Code = half scale − 3 dB
R
AB
= 5 kΩ 4 MHz
R
AB
= 10 kΩ 2 MHz
R
AB
= 80 kΩ 200 kHz
Total Harmonic Distortion THD V
A
= V
DD
/2 + 1 V rms,
V
B
= V
DD
/2, f = 1 kHz,
code = half scale
R
AB
= 5 kΩ −75 dB
R
AB
= 10 kΩ −80 dB
R
AB
= 80 kΩ −85 dB
V
W
Settling Time t
s
V
A
= 5 V, V
B
= 0 V,
±0.5 LSB error band
µs
R
AB
= 5 kΩ
2.5
µs
R
AB
= 10 kΩ 3 µs
R
AB
= 80 kΩ 10 µs
Resistor Noise Density e
N_WB
Code = half scale, T
A
= 25°C,
f = 100 kHz
R
AB
= 5 kΩ
7
nV/√Hz
R
AB
= 10 kΩ 9 nV/√Hz
R
AB
= 80 kΩ 20 nV/√Hz
FLASH/EE MEMORY RELIABILITY
3
Endurance
10
T
A
= 25°C 1 MCycles
100 kCycles
Data Retention
11
50 Years
1
Typical values represent average readings at 25°C, VDD = 5 V, V
SS
= 0 V, and V
LOGIC
= 5 V.
2
Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to 0.75 × V
DD
/R
AB
.
3
Guaranteed by design and characterization, not subject to production test.
4
INL and DNL are measured at V
WB
with the RDAC configured as a potentiometer divider similar to a voltage output DAC. V
A
= V
DD
and V
B
= 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6
Different from operating current; supply current for NVM program lasts approximately 30 ms.
7
Different from operating current; supply current for NVM read lasts approximately 20 µs.
8
P
DISS
is calculated from (I
DD
× V
DD
) + (I
LOGIC
× V
LOGIC
).
9
All dynamic characteristics use V
DD
= 5.5 V, and V
LOGIC
= 5 V.
10
Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C.
11
Retention lifetime equivalent at junction temperature (T
J
) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV
derates with junction temperature in the Flash/EE memory.