Datasheet

AD5110/AD5112/AD5114 Data Sheet
Rev. B | Page 20 of 28
INPUT SHIFT REGISTER
For the AD5110/AD5112/AD5114, the input shift register is
16 bits wide (see Figure 2). The 16-bit word consists of five
unused bits (should be set to zero), followed by three control
bits, and eight RDAC data bits. If the RDAC register is read from
or written to in the AD5112, Bit DB0 is a don’t care. The RDAC
register is read from or written to in the AD5114, Bit DB0 and
DB1 are don’t cares. Data is loaded MSB first (Bit DB15).
The three control bits determine the function of the software
command (Table 10). Figure 3 shows a timing diagram of a
typical AD5110/AD5112/AD5114 write sequence.
The command bits (Cx) control the operation of the digital
potentiometer and the internal EEPROM. The data bits (Dx)
are the values that are loaded into the decoded register.
Table 10. Command Operation Truth Table
Command
Number
Command Data
1
DB10 DB8 DB7 DB0
C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 Operation
0 0 0 0 X X X X X X X X No operation
1 0 0 1 X X X X X X X X Write contents of RDAC register to EEPROM
2 0 1 0 7
MSB
6 5 4 3 2 1
2
0
2, 3
LSB
Write contents of serial register data to RDAC
1 0 0 0 0 0 0 0 Top scale
1 1 1 1 1 1 1 1 Bottom scale
3 0 1 1 X X X X X X X A0 Software shutdown
0: shutdown off
1: shutdown on
4 1 0 0 X X X X X X X X Software reset: refresh RDAC register with EEPROM
5 1 0 1 X X X X X X X X Read contents of RDAC register
6 1 1 0 X X X X X X A1 A0 Read contents of EEPROM
A1 A0 Data
0
0
Wiper position saved
0 1 Resistor tolerance
1
X is don’t care.
2
In the AD5114, this bit is a don’t care.
3
In the AD5112, this bit is a don’t care.