Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - Digital potentiometer linear Permanent LFCSP 8 UD

Single-Channel, 128-/64-/32-Position, I

C, ±8%

Resistor Tolerance, Nonvolatile Digital Potentiometer

Data Sheet

AD5110/AD5112/AD5114

Rev. B Document Feedback

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FEATURES

Nominal resistor tolerance error: ±8% maximum

Wiper current: ±6 mA

Rheostat mode temperature coefficient: 35 ppm/°C

Low power consumption: 2.5 µA max @ 2.7 V and 125°C

Wide bandwidth: 4 MHz (5 kΩ option)

Power-on EEPROM refresh time < 50 μs

50-year typical data retention at 125°C

1 million write cycles

2.3 V to 5.5 V analog supply operation

1.8 V to 5.5 V logic supply operation

Wide operating temperature: −40°C to +125°C

Thin, 2 mm × 2 mm × 0.55 mm 8-lead LFCSP package

APPLICATIONS

Mechanical potentiometer replacement

Portable electronics level adjustment

Audio volume control

Low resolution DAC

LCD panel brightness and contrast control

Programmable voltage to current conversion

Programmable filters, delays, time constants

Feedback resistor programmable power supply

Sensor calibration

FUNCTIONAL BLOCK DIAGRAM

POWER-ON

RESET

LOGIC

DATA

SDA

SCL

EEPROM

AD5110/AD5112/AD5114

RDAC

GND

SERIAL

INTERFACE

09582-001

Figure 1.

Table 1. ±8% Resistance Tolerance Family

Model Resistance (kΩ) Position Interface

AD5110 10, 80 128 I

AD5111 10, 80 128 Up/down

AD5112

5, 10, 80

AD5113 5, 10, 80 64 Up/down

AD5116 5, 10, 80 64 Push-button

AD5114 10, 80 32 I

AD5115 10, 80 32 Up/down

GENERAL DESCRIPTION

The AD5110/AD5112/AD5114 provide a nonvolatile solution

for 128-/64-/32-position adjustment applications, offering

guaranteed low resistor tolerance errors of ±8% and up to

±6 mA current density in the A, B, and W pins. The low resistor

tolerance, low nominal temperature coefficient and high

bandwidth simplify open-loop applications, as well as tolerance

matching applications.

The new low wiper resistance feature minimizes the wiper

resistance in the extremes of the resistor array to only 45 Ω,

typical.

The wiper settings are controllable through an I

C-compatible

digital interface that is also used to readback the wiper register

and EEPROM content. Resistor tolerance is stored within

EEPROM, providing an end-to-end tolerance accuracy of 0.1%.

The AD5110/AD5112/AD5114 are available in a 2 mm × 2 mm

LFCSP package. The parts are guaranteed to operate over the

extended industrial temperature range of −40°C to +125°C.

Summary of content (28 pages)

PAGE 1
Single-Channel, 128-/64-/32-Position, I2C, ±8% Resistor Tolerance, Nonvolatile Digital Potentiometer Data Sheet AD5110/AD5112/AD5114 FEATURES FUNCTIONAL BLOCK DIAGRAM VLOGIC VDD AD5110/AD5112/AD5114 POWER-ON RESET A W DATA SDA SCL EEPROM I2C SERIAL INTERFACE DATA B RDAC REGISTER 09582-001 Nominal resistor tolerance error: ±8% maximum Wiper current: ±6 mA Rheostat mode temperature coefficient: 35 ppm/°C Low power consumption: 2.5 µA max @ 2.
PAGE 2
AD5110/AD5112/AD5114 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 19 Applications ....................................................................................... 1 RDAC Register and EEPROM .................................................. 19 Functional Block Diagram .................................................
PAGE 3
Data Sheet AD5110/AD5112/AD5114 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—AD5110 10 kΩ and 80 kΩ versions: VDD = 2.3 V to 5.5 V, VLOGIC = 1.8 V to VDD, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted. Table 2.
PAGE 4
AD5110/AD5112/AD5114 Parameter POWER SUPPLIES Single-Supply Power Range Logic Supply Range Positive Supply Current EEMEM Store Current3, 6 EEMEM Read Current3, 7 Logic Supply Current Power Dissipation 8 Power Supply Rejection3 DYNAMIC CHARACTERISTICS3, 9 Bandwidth Total Harmonic Distortion VW Settling Time Resistor Noise Density FLASH/EE MEMORY RELIABILITY3 Endurance 10 Data Sheet Symbol Test Conditions/Comments Min Typ 1 Max Unit 0.75 5.5 VDD 3.5 2.5 2.
PAGE 5
Data Sheet AD5110/AD5112/AD5114 ELECTRICAL CHARACTERISTICS—AD5112 5 kΩ, 10 kΩ, and 80 kΩ versions: VDD = 2.3 V to 5.5 V, VLOGIC = 1.8 V to VDD, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted. Table 3.
PAGE 6
AD5110/AD5112/AD5114 Parameter POWER SUPPLIES Single-Supply Power Range Logic Supply Range Positive Supply Current EEMEM Store Current3, 6 EEMEM Read Current3, 7 Logic Supply Current Power Dissipation 8 Power Supply Rejection3 DYNAMIC CHARACTERISTICS3, 9 Bandwidth Total Harmonic Distortion VW Settling Time Resistor Noise Density FLASH/EE MEMORY RELIABILITY3 Endurance 10 Data Sheet Symbol Test Conditions/Comments Min Typ 1 Max Unit 0.75 5.5 VDD 3.5 2.5 2.
PAGE 7
Data Sheet AD5110/AD5112/AD5114 ELECTRICAL CHARACTERISTICS—AD5114 10 kΩ and 80 kΩ versions: VDD = 2.3 V to 5.5 V, VLOGIC = 1.8 V to VDD, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted. Table 4.
PAGE 8
AD5110/AD5112/AD5114 Parameter POWER SUPPLIES Single-Supply Power Range Logic Supply Range Positive Supply Current EEMEM Store Current3, 6 EEMEM Read Current3, 7 Logic Supply Current Power Dissipation 8 Power Supply Rejection3 DYNAMIC CHARACTERISTICS3, 9 Bandwidth Total Harmonic Distortion VW Settling Time Resistor Noise Density FLASH/EE MEMORY RELIABILITY3 Endurance 10 Data Sheet Symbol Test Conditions/Comments Min Typ 1 Max Unit 0.75 5.5 VDD 3.5 2.5 2.
PAGE 9
Data Sheet AD5110/AD5112/AD5114 INTERFACE TIMING SPECIFICATIONS VLOGIC = 1.8 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 5.
PAGE 10
AD5110/AD5112/AD5114 Data Sheet SHIFT REGISTER AND TIMING DIAGRAM DB7 (MSB) 0 0 0 0 C2 C1 C0 D7 D6 D5 D4 D3 D2 D0 D1 09582-002 0 DB0 (LSB) DATA BITS CONTROL BITS Figure 2. Input Register Content t11 t12 t6 t2 SCL t1 t6 t4 t5 t8 t10 t3 t9 P t7 S S Figure 3. 2-Wire Serial Interface Timing Diagram Rev.
PAGE 11
Data Sheet AD5110/AD5112/AD5114 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 6.
PAGE 12
AD5110/AD5112/AD5114 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS A 2 W 3 B 4 AD5110/ AD5112/ AD5114 TOP VIEW (Not to Scale) 8 VLOGIC 7 SDA 6 SCL 5 GND NOTES 1. THE EXPOSED PAD IS INTERNALLY FLOATING. 09582-004 VDD 1 Figure 4. Pin Configuration Table 8. Pin Function Descriptions Pin No. 1 Mnemonic VDD 2 3 4 5 6 A W B GND SCL 7 SDA 8 VLOGIC Description Positive Power Supply; 2.3 V to 5.5 V. This pin should be decoupled with 0.1 µF ceramic capacitors and 10 µF capacitors.
PAGE 13
Data Sheet AD5110/AD5112/AD5114 TYPICAL PERFORMANCE CHARACTERISTICS 0.10 0.02 10kΩ, 10kΩ, 10kΩ, 80kΩ, 80kΩ, 80kΩ, 0.08 10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C 80kΩ, –40°C 80kΩ, +25°C 80kΩ, +125°C 0.01 0 –0.01 0.04 R-DNL (LSB) R-INL (LSB) 0.06 –40°C +25°C +125°C –40°C +25°C +125°C 0.02 0 –0.02 –0.03 –0.04 –0.02 0.08 0.
PAGE 14
AD5110/AD5112/AD5114 Data Sheet 0.02 0.08 10kΩ, 10kΩ, 10kΩ, 80kΩ, 80kΩ, 80kΩ, 0.06 0.04 –40°C +25°C +125°C –40°C +25°C +125°C 0.01 0 –0.01 DNL (LSB) INL (LSB) 0.02 0 –0.02 –0.02 –0.03 –0.04 –0.04 0.02 5kΩ, –40°C 5kΩ, +25°C 5kΩ, +125°C 10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C 80kΩ, –40°C 80kΩ, +25°C 80kΩ, +125°C –0.05 09582-012 119 127 112 98 105 91 84 77 70 63 56 80kΩ, +25°C 80kΩ, –40°C –0.
PAGE 15
Data Sheet AD5110/AD5112/AD5114 0.12 800 700 SUPPLY CURRENT, ILOGIC (mA) 400 300 200 2.3V AVERAGE OF I DD 2.3V AVERAGE OF I LOGIC 3.3V AVERAGE OF I DD 3.3V AVERAGE OF I LOGIC 5.0V AVERAGE OF I DD 5.0V AVERAGE OF I LOGIC 0.08 0.06 0.04 0.02 0 0 –25 –10 5 35 50 65 20 TEMPERATURE (°C) 80 95 110 125 –0.02 09582-017 –100 –40 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 DIGITAL INPUT VOLTAGE (V) Figure 17. Supply Current vs. Temperature Figure 20. Supply Current (ILOGIC) vs.
PAGE 16
AD5110/AD5112/AD5114 Data Sheet 80 0 0x40 (0x20) [0x10] 60 0x04 (0x02) [0x01] –30 0x02 (0x01) [0x00] –40 0x01 (0x00) –50 80k + 150pF 80k + 250pF 5k + 0pF 5k + 75pF 5k + 150pF 10k + 0pF 50 40 30 0x00 –60 5k + 250pF 10k + 75pF 10k + 150pF 10k + 250pF 80k + 0pF 80k + 75pF 70 BANDWIDTH (MHz) GAIN (dB) –10 0x20 (0x10) [0x08] 0x10 (0x08) [0x04] –20 0x08 (0x04) [0x02] 20 –70 10 1M 100k FREQUENCY (Hz) 0 09582-023 –80 10k –20 –30 –40 –60 AD5110 RAB = 10kΩ –70 FULL SCALE HALF SCALE QUARTER SCA
PAGE 17
Data Sheet AD5110/AD5112/AD5114 0.25 0.2 0.1 VOLTAGE (mV) 0.20 0.15 0.10 0 –0.1 0.05 –0.2 0 –0.3 –0.05 –0.4 3 7 5 TIME (µs) 9 –0.5 10kΩ 80kΩ 5kΩ 0 0.6 Figure 29. Maximum Transition Glitch 0 1.0 –10 CUMULATIVE PROBABILITY 1.2 0.0015 0.6 0.0010 0.4 0.0005 300 400 500 –40 –70 09582-051 200 –30 –60 0 100 600 RESISTOR DRIFT (ppm) 1k Figure 30.
PAGE 18
AD5110/AD5112/AD5114 Data Sheet TEST CIRCUITS Figure 35 to Figure 40 define the test conditions used in the Specifications section. NC IW VA B A W V+ ~ VMS B 09582-035 Figure 35. Resistor Position Nonlinearity Error (Rheostat Operation: R-INL, R-DNL) PSS (%/%) = VMS Figure 38. Power Supply Sensitivity (PSS, PSRR) +15V A V+ = VDD 1LSB = V+/2N DUT A B W VIN W DUT B OFFSET GND VMS 09582-036 V+ Figure 39. Gain and Phase vs. Frequency GND VDD GND VDD DUT A 0.
PAGE 19
Data Sheet AD5110/AD5112/AD5114 THEORY OF OPERATION The AD5110/AD5112/AD5114 digital programmable resistors are designed to operate as true variable resistors for analog signals within the terminal voltage range of GND < VTERM < VDD. The resistor wiper position is determined by the RDAC register contents. The RDAC register acts as a scratchpad register that allows unlimited changes of resistance settings. The RDAC register can be programmed with any position setting using the I2C interface.
PAGE 20
AD5110/AD5112/AD5114 Data Sheet INPUT SHIFT REGISTER The three control bits determine the function of the software command (Table 10). Figure 3 shows a timing diagram of a typical AD5110/AD5112/AD5114 write sequence. For the AD5110/AD5112/AD5114, the input shift register is 16 bits wide (see Figure 2). The 16-bit word consists of five unused bits (should be set to zero), followed by three control bits, and eight RDAC data bits.
PAGE 21
Data Sheet AD5110/AD5112/AD5114 WRITE OPERATION these data bytes are acknowledged by the AD5110/AD5112/ AD5114. A stop condition follows. The write operations for the AD5110/AD5112/AD5114 are shown in Figure 41, Figure 42, and Figure 43. When writing to the AD5110/AD5112/AD5114, the user must begin with a start command followed by an address byte (R/W = 0), after which the AD5110/AD5112/AD5114 acknowledge that it is prepared to receive data by pulling SDA low.
PAGE 22
AD5110/AD5112/AD5114 Data Sheet 1 9 1 9 SCL 1 0 SDA 0 1 1 A1 A0 R/W 0 0 0 0 0 C2 C1 C0 ACK. BY AD5114 ACK. BY AD5114 START BY MASTER FRAME 2 MOST SIGNIFICANT DATA BYTE FRAME 1 SERIAL BUS ADDRESS BYTE 9 9 1 SCL (CONTINUED) D5 D4 D3 D2 D1 D0 0 0 ACK. BY STOP BY AD5114 MASTER FRAME 3 LEAST SIGNIFICANT DATA BYTE 09582-043 SDA (CONTINUED) Figure 43.
PAGE 23
Data Sheet AD5110/AD5112/AD5114 the RDAC register, EEPROM memory. The user can then read back the data. This begins with a start command followed by an address byte (R/W = 1), after which the device acknowledges that it is prepared to transmit data by pulling SDA low. Two bytes of data are then read from the device, which are both acknowledged by the master, as shown in Figure 45. A stop condition follows.
PAGE 24
AD5110/AD5112/AD5114 Data Sheet RDAC ARCHITECTURE PROGRAMMING THE VARIABLE RESISTOR To achieve optimum performance, Analog Devices, Inc., has patented the RDAC segmentation architecture for all the digital potentiometers. In particular, the AD5110/AD5112/AD5114 employ a two-stage segmentation approach as shown in Figure 46. The AD5110/AD5112/AD5114 wiper switch is designed with the transmission gate CMOS topology and with the gate voltage derived from VDD.
PAGE 25
Data Sheet AD5110/AD5112/AD5114 Similar to the mechanical potentiometer, the resistance of the RDAC between the W terminal and the A terminal also produces a digitally controlled complementary resistance, RWA. RWA also gives a maximum of 8% absolute resistance error. RWA starts at the maximum resistance value and decreases as the data loaded into the latch increases. The general equations for this operation are Table 11.
PAGE 26
AD5110/AD5112/AD5114 Data Sheet TERMINAL VOLTAGE OPERATING RANGE The AD5110/AD5112/AD5114 are designed with internal ESD diodes for protection. These diodes also set the voltage boundary of the terminal operating voltages. Positive signals present on Terminal A, Terminal B, or Terminal W that exceed VDD are clamped by the forward-biased diode. There is no polarity constraint between VA, VW, and VB, but they cannot be higher than VDD or lower than GND.
PAGE 27
Data Sheet AD5110/AD5112/AD5114 OUTLINE DIMENSIONS 1.70 1.60 1.50 2.00 BSC SQ 0.50 BSC 8 5 PIN 1 INDEX AREA 1.10 1.00 0.90 EXPOSED PAD 0.425 0.350 0.275 1 4 TOP VIEW 0.60 0.55 0.50 BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM 0.30 0.25 0.20 PIN 1 INDICATOR (R 0.15) 07-11-2011-B SEATING PLANE 0.175 REF 0.20 REF Figure 51. 8-Lead Frame Chip Scale Package[LFCSP_UD] 2.00 mm × 2.
PAGE 28
AD5110/AD5112/AD5114 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09582-0-11/12(B) Rev.