Datasheet

Data Sheet AD5111/AD5113/AD5115
Rev. | Page 21 of 24
POWER-UP SEQUENCE
Because of the ESD protection diodes that limit the voltage
compliance at the A, B, and W terminals (see Figure 45), it is
important to power on V
DD
before applying any voltage to the
A, B, and W terminals. Otherwise, the diodes are forward-
biased such that V
DD
is powered on unintentionally and can
affect other parts of the circuit. Similarly, V
DD
should be
powered down last. The ideal power-on sequence is in the
following order: GND, V
DD
, and V
A
/V
B
/V
W
. The order of
powering V
A
, V
B
, V
W
and the digital inputs is not important as
long as they are powered on after V
DD
.
GND
V
DD
A
W
B
09654-046
Figure 45. Maximum Terminal Voltages Set by V
DD
and GND
LAYOUT AND POWER SUPPLY BIASING
It is always a good practice to use compact, minimum lead
length layout design. The leads to the input should be as direct
as possible with a minimum conductor length. Ground paths
should have low resistance and low inductance. It is also good
practice to bypass the power supplies with quality capacitors.
Apply low equivalent series resistance (ESR) 1 μF to 10 μF
tantalum or electrolytic capacitors at the supplies to minimize
any transient disturbance and to filter low frequency ripple.
Figure 46 illustrates the basic supply bypassing configuration
for the AD5111/AD5113/AD5115.
V
DD
V
DD
+
GND
C1
0.1µF
C2
10µF
AGND
AD5111/
AD5113/
AD5115
09654-047
Figure 46. Power Supply Bypassing
A