Datasheet

AD5100
Rev. A | Page 7 of 36
TIMING SPECIFICATIONS
Table 3.
Parameter Description Min Typ Max Unit
I
2
C INTERFACE TIMING CHARACTERISTICS
1, 2
f
SCL
SCL clock frequency 400 kHz
t
1
t
BUF
, bus free time between start and stop 1.3 μs
t
2
t
HD;STA
, hold time after (repeated) start condition; after this
period, the first clock is generated
0.6 μs
t
3
t
LOW
, low period of SCL clock 1.3 μs
t
4
t
HIGH
, high period of SCL clock 0.6 50 μs
t
5
t
SU;STA
, setup time for start condition 0.6 μs
t
6
t
HD;DAT
, data hold time 0.9 μs
t
7
t
SU;DAT
, data setup time 0.1 μs
t
8
t
F
, fall time of both SDA and SCL signals 0.3 μs
t
9
t
R
, rise time of both SDA and SCL signals 0.3 μs
t
10
t
SU;STO
, setup time for stop condition 0.6 μs
1
Guaranteed by design and not subject to production test.
2
See Figure 2.
SCL
t
2
t
3
t
4
t
7
t
5
t
10
t
2
t
8
t
1
PS SP
t
9
t
6
t
8
S
D
A
05692-002
t
9
Figure 2. Digital Interface Timing Diagram