Datasheet

AD5100
Rev. A | Page 25 of 36
Register
Address
Read/
Write
Permanently
Settable Register Name and Bit Description
NonOTP Power-On
Default
1
0x16 R/W No Special function 1 0x00
Bit No. Description
[0] Reserved
[1] Reserved
[2]
0: software assertion of SHDN
pin is inactive
1: pulls SHDN
pin low
[3] 0: override of permanent settings inactive
1: override of permanent settings active
[7:4] Reserved
0x17 R/W No Special function 2 0x00
Bit No. Description
[0] 0: software power-down of AD5100 inactive
1: software power-down of AD5100 active
2
[7:1] Reserved
0x18 R/W No Disable special functions
3
0x00
Bit No. Description
[0]
0: allows override of any of the registers in memory except
Register 0x16 Bit[2:0] and Register 0x17 Bit[0]
1: disables override of any of the registers in memory except
Register 0x16 Bit[2:0] and Register 0x17 Bit[0]
[1] Reserved
[2] Reserved
[3] 0: allows software power-down function
1: disables software power-down function
[4]
0: allows software assertion of SHDN
pin
1: disables software assertion of SHDN
pin
[7:5] Reserved
0x19
Read-
only
No
Fault detect and status
(Bits[3:0] are level triggered bits that indicate the current state of the
comparators monitoring the V
1MON
and V
2MON
input pins; Bits[6:4] are edge
triggered fault detection bits that indicate what error conditions were present
when a SHDN event occurred)
0x40
Bit No. Description
[0] 1 = V
2MON
input < V
2MON
off threshold
[1] 1 = V
2MON
input > V
2MON
on threshold
[2] 1 = V
1MON
input < V
1MON
UV threshold
[3] 1 = V
1MON
input > V
1MON
OV threshold
[6:4] 000: none
001: V
1MON
UV only
010: V
1MON
OV only
011: never occurred
100: V
2MON
below off only (default)
101: V
1MON
UV and V
2MON
below off both occurred
110: V
1MON
OV and V
2MON
below off both occurred
111: never occurred
[7] Reserved
1
Default settings of AD5100-0 evaluation model only.
2
V
2MON
must be 0 V (that is, V
2MON
must be configured in edge sensitive mode) for software power-down.
3
These register bits are set only. To clear them, the AD5100 must be power cycled. In some cases, the AD5100 can be connected to an I
2
C bus with lots of activity.
Setting these bits is an added means of ensuring that any erroneous activity on the bus does not cause AD5100 special functions to become active.