Datasheet

AD5100
Rev. A | Page 24 of 36
Register
Address
Read/
Write
Permanently
Settable Register Name and Bit Description
NonOTP Power-On
Default
1
0x09 R/W Yes
V
2MON
turn-on triggered SHDN hold (t
2SD_HOLD
)
0x00 (10 ms)
Bit No. Description
[2:0]
Three bits used to program V
2MON
t
ON
triggered SHDN hold time
[7:3] Reserved
0x0A R/W Yes
V
2MON
turn-off triggered SHDN delay (t
2SD_DELAY
)
0x00 (100 ms)
Bit No. Description
[2:0]
Three bits used to program V
2MON
t
OFF
triggered SHDN delay time
[7:3] Reserved
0x0B R/W Yes
RESET
hold (t
RS_HOLD
)
0x00 (200 ms)
Bit No. Description
[2:0]
Three bits used to program RESET
hold time
[7:3] Reserved
0x0C R/W Yes Watchdog timeout (t
WD
) 0x00 (1500 ms)
Bit No. Description
[2:0] Three bits used to program watchdog timeout time
[7:3] Reserved
0x0D R/W Yes
RESET
configuration
0x00
Bit No. Description
[0]
0: RESET
is active when SHDN is active
1: RESET
is not active when SHDN is active
[1]
0: RESET
active low
1: RESET
active high
[2]
0: enables V
4MON
under threshold, causing RESET
1: prevents V
4MON
under threshold from causing RESET (for V
4OUT
applications)
[3]
0: floating WDI does not activate RESET
1: floating WDI activates RESET
[7:4] Reserved
0x0E R/W Yes
SHDN
rail voltage configuration
0x00
Bit No. Description
[2:0] Reserved
[3]
0: SHDN
rail = V
1MON
1: SHDN
rail = V
REG
[7:4] Reserved
0x0F R/W Yes Watchdog mode 0x00
Bit No. Description
[2:0] Reserved
[3] 0: standard mode
1: advanced mode
[7:4] Reserved
0x15 R/W Yes Program lock (inhibit further programming) 0x00
Bit No. Description
[2:0] Reserved
[3] Reserved
[7:4] Reserved