Datasheet

AD5100
Rev. A | Page 17 of 36
Standard Watchdog Mode
In the default standard watchdog mode, if WDI remains either
high or low for longer than the timeout period, t
WD
, a
RESET
pulse is generated in an attempt to allow the system processor
to reestablish the WDI signal. The
RESET
pulses continue
indefinitely until a valid watchdog signal, a rising or falling edge
signal at the WDI, is received. The internal watchdog timer
clears whenever a reset is asserted. The standard WDI and
RESET
timing diagrams are shown in . Figure 13
Advanced Watchdog Mode
The AD5100 can be programmed into an advanced watchdog
mode. In this mode, if WDI remains either high or low for longer
than the timeout period, t
WD
, a
RESET
pulse is generated, as per
standard mode. However, if the WDI input remains inactive after
three such
RESET
pulses, concurrent with the fourth
RESET
pulse,
SHDN
is also asserted.
SHDN
is released after 1 second. These
actions repeat indefinitely (unless action is taken by the user), if
the processor is not responding. The advanced WDI and
RESET
timing diagrams are shown in . Figure 14
0
5692-013
t
WDI
t
WD
t
WDR
t
WD
t
WDR
WDI
RESET PULSE CONTINUOUS PULSES UNTIL WATCHDOG AWAKES
RESET
t
WDR
= WATCHDOG-INITIATED RESET PULSE WIDTH
t
WDI
= WATCHDOG PULSE WIDTH
t
WD
= WATCHDOG PROGRAMMABLE TIME
Figure 13. Standard Watchdog—Pulsing Reset Until Watchdog Awakes
05692-014
t
WDI
t
WD
t
WDI
t
WD_SHDN
t
WD
t
WDR
3 RESET PULSES1 RESET PULSE
SHUTDOWN AT 4TH RESET PULSE RELEASE AFTER 1s
WDI
RESET
SHDN
Figure 14. Advanced Watchdog—
SHDN
Asserted After Three Trials of Resetting the Watchdog (
SHDN
Released After 1 Second and the Cycle Repeats)