Datasheet

AD5100
Rev. A | Page 16 of 36
V
4MON
V
4MON
is a low voltage monitoring input that controls the
RESET
function of an external device or provides a comparator output,
V
4OUT
. The V
4MON
pin is monitored by a comparator to detect an
undervoltage condition. It is designed with 5% hysteresis.
When the V
4MON
input drops below the programmed UV thresh-
old, the comparator becomes active immediately, indicating that
a UV condition has occurred. Due to hysteresis, the V
4MON
input
must be brought above the programmed UV threshold by 5%
before the comparator becomes inactive, indicating that the UV
condition has gone away (see Figure 11).
0
5692-012
V
4MON
V
4MON_UV
UV
COMPARATOR
INACTIVE
UV
COMPARATOR
INACTIVE
HYSTERESIS
Figure 11. V
4MON
Hysteresis
The V
4MON
comparator is used to control the V
4OUT
pin and (in
conjunction with a hold timer) to control the
RESET
pin. To
configure V
4MON
to control the
RESET
pin, set Register 0x0D[3]
to 0. Setting this bit to 1 prevents V
4MON
from causing
RESET
to
activate. The default setting is V
4MON
does not cause
RESET
to
activate.
V
4MON
input voltage range is up to 30 V. It has an 8-step
programmable reset threshold (Register 0x06) from 1.67 V
to 7.96 V, with an 8-step 0.1 ms to 200 ms reset hold time
(t
RS_HOLD
).
The V
4MON
,
RESET
, and V
4OUT
timing diagrams are shown in
. The range of thresholds is shown in , and the
programming code for the selected threshold is found in .
The default monitoring threshold is 7.54 V. Similarly, the range
of reset hold time is shown in , and the programming
code of the selected timing is found in .
Figure 12 Table 6
Table 8
Table 8
Table 9
V
4MON
exhibits typical input resistance of 675 kΩ that users
should take into account for loading effect.
WATCHDOG INPUT
The watchdog input (WDI) circuit attempts to reset the system
to a known good state if a software or hardware glitch renders
the system processor inactive for a duration that is longer than
the timeout period. The timeout period, t
WD
, is programmable
in eight steps from 100 ms to 2000 ms. The watchdog circuit is
independent of any CPU clock that the watchdog is monitoring.
The range of watchdog timeout is shown in Table 8, and the
programming code of the selected timeout is found in Table 9.
The default timeout is 1500 ms.
The watchdog is disabled during power-up. WDI starts monitor-
ing once
RESET
is high. The AD5100 provides a standard or
advanced watchdog monitoring function. Register 0x0F[3] sets
the watchdog function to either standard or advanced mode.
This bit can be fixed in OTP memory.
• Register 0x0F[3] = 0: standard watchdog mode (Default)
• Register 0x0F[3] = 1: advanced watchdog mode
V
4MON
V
4MON
V
4OUT
t
GLITCH
RESET
NOTES
1. * = PROGRAMMABLE.
2. MOST APPLICATIONS USING V
4OUT
REQUIRE DISABLING OF V
4MON
TRIGGERED RESET.
05692-011
t
RS_HOLD*
t
RS_HOLD*
t
RS_DELAY
t
RS_DELAY
Figure 12. V
4MON
,
RESET
, and V
4OUT
Timing Diagrams