Datasheet

AD5066
Rev. A | Page 5 of 24
TIMING CHARACTERISTICS
All input signals are specified with t
R
= t
F
= 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2, V
DD
= 2.7 V to
5.5 V, all specifications T
MIN
to T
MAX
, unless otherwise noted. See Figure 2.
Table 4.
Parameter
1
Symbol Min Typ Max Unit
SCLK Cycle Time t
1
20 ns
SCLK High Time t
2
10 ns
SCLK Low Time t
3
10 ns
SYNC
to SCLK Falling Edge Set-Up Time t
4
17 ns
Data Set-Up Time t
5
5 ns
Data Hold Time t
6
5 ns
SCLK Falling Edge to
SYNC
Rising Edge t
7
5 30 ns
Minimum
SYNC
High Time t
8
Single Channel Update 3 µs
All Channel Update 8 µs
SYNC
Rising Edge to SCLK Fall Ignore t
9
17 ns
LDAC
Pulse Width Low t
10
20 ns
SCLK Falling Edge to
LDAC
Rising Edge t
11
20 ns
CLR
Pulse Width Low t
12
10 ns
SCLK Falling Edge to
LDAC
Falling Edge t
13
10 ns
CLR
Pulse Activation Time t
14
10.6 µs
1
Maximum SCLK frequency is 50 MHz. Guaranteed by design and characterization; not production tested.
t
4
t
3
SCLK
SYNC
DIN
t
1
t
2
t
5
t
6
t
7
t
8
DB31
t
9
t
10
t
11
LDAC
1
LDAC
2
t
13
1
ASYNCHRONOUS LDAC UPDATE MODE.
2
SYNCHRONO U
S LDAC UPDATE MODE.
CLR
t
12
t
1 4
V
OUT
DB0
06845-003
Figure 2. Serial Write Operation