Datasheet

AD5066
Rev. A | Page 3 of 24
SPECIFICATIONS
V
DD
= 2.7 V to 5.5 V, 2.0 V ≤ V
REF
A, V
REF
B, V
REF
C, V
REF
D ≤ V
DD
− 0.4 V, all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
A Grade
1
B
Grade
1
Un
it Conditions/Comments
Min Typ Max Min Typ Max
STATIC PERFORMANCE
2
Resolution 16 16 Bits
Relative Accuracy (INL) ±0.5 ±4 ±0.5 ±1 LSB T
A
= −40°C to +105°C
±0.5 ±4 ±0.5 ±2 T
A
= −40°C to +125°C
Differential Nonlinearity (DNL) ±0.2 ±1 ±0.2 ±1 LSB
Total Unadjusted Error (TUE) ±0.1 ±0.8 ±0.1 ±0.8 mV V
DD
= 2.7 V, V
REF
= 2 V
Zero-Code Error 0.05 0.1 0.05 0.1 mV All 0s loaded to the DAC register
Zero-Code Error Drift
3
±0.5 ±0.5 µV/°C
Full-Scale Error ±0.01 ±0.05 ±0.01 ±0.05 % FSR All 1s loaded to the DAC register
Gain Error ±0.005 ±0.05 ±0.005 ±0.05 % FSR
Gain Error Drift
3
±0.5 ±0.5 ppm ppm of FSR/°C
DC Crosstalk
3
1 5 1 5 μV Due to single-channel full-scale
output change
5 25 5 25 μV Due to powering down (per channel)
OUTPUT CHARACTERISTICS
3
Output Voltage Range 0 V
REF
0 V
REF
V
DC Output Impedance (Normal
Mode)
8 8 kΩ Output impedance tolerance ± 10%
DC Output Impedance DAC in power-down mode
Output Connected to 100 kΩ
Network
100 100 kΩ Output impedance tolerance ± 20 kΩ
Output Connected to 1 kΩ
Network
1 1 kΩ Output impedance tolerance ± 400 Ω
Power-Up Time
4
2.9 2.9 µs
DC PSRR −120 −120 dB V
DD
± 10%, DAC = full scale
REFERENCE INPUTS
Reference Input Range 2 V
DD
− 0.4 2 V
DD
− 0.4 V
Reference Current 0.002 ±1 0.002 ±1 µA Per DAC channel
Reference Input Impedance 40 40 MΩ Per DAC channel
LOGIC INPUTS
3
Input Current
5
±1 ±1 µA
Input Low Voltage, V
INL
0.8 0.8 V
Input High Voltage, V
INH
2.2 2.2 V
Pin Capacitance 4 4 pF
POWER REQUIREMENTS
V
DD
2.7 5.5 2.7 5.5 V All digital inputs at 0 V or V
DD
DAC active, excludes load current
I
DD
V
IH
= V
DD
and V
IL
= GND
Normal Mode
6
2.5 3 2.5 3 mA
All Power-Down Modes
7
0.4 0.4 µA
1
Temperature range is −40°C to +125°C, typical at 25°C.
2
Linearity calculated using a code range of 0 to 65,535; output unloaded.
3
Guaranteed by design and characterization; not production tested.
4
Time taken to exit power-down mode and enter normal mode, 32
nd
clock edge to 90% of DAC midscale value, output unloaded.
5
Current flowing into individual digital pins. VDD = 5.5 V; VREF = 4.096 V; Code = midscale.
6
Interface inactive. All DACs active. DAC outputs unloaded.
7
All four DACs powered down.