Datasheet

AD5025/AD5045/AD5065
Rev. 0 | Page 5 of 28
TIMING CHARACTERISTICS
All input signals are specified with t
R
= t
F
= 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2. See Figure 3 and
Figure 4. V
DD
= 4.5 V to 5.5 V. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 4.
Parameter Symbol Min Typ Max Unit
SCLK Cycle Time t
1
1
20 ns
SCLK High Time t
2
10 ns
SCLK Low Time t
3
10 ns
SYNC to SCLK Falling Edge Setup Time
t
4
16.5 ns
Data Setup Time t
5
5 ns
Data Hold Time t
6
5 ns
SCLK Falling Edge to SYNC Rising Edge
t
7
0 30 ns
Minimum SYNC High Time (Single Channel Update)
t
8
2 µs
Minimum SYNC High Time (All Channel Update)
t
8
4 µs
SYNC Rising Edge to SCLK Fall Ignore
t
9
17 ns
LDAC Pulse Width Low
t
10
20 ns
SCLK Falling Edge to LDAC Rising Edge
t
11
20 ns
CLR Pulse Width Low
t
12
10 ns
SCLK Falling Edge to LDAC Falling Edge
t
13
10 ns
CLR Pulse Activation Time
t
14
10.6 µs
SCLK Rising Edge to SDO Valid t
15
2, 3
22 ns
SCLK Falling Edge to SYNC Rising Edge
t
16
2
5 30 ns
SYNC Rising Edge to SCLK Rising Edge
t
17
2
8 ns
SYNC Rising Edge to LDAC/CLR/PDL Falling Edge (Single Channel Update)
t
18
2
2 µs
SYNC Rising Edge to LDAC/CLR/PDL Falling Edge (All Channel Update)
t
18
2
4 µs
PDL Minimum Pulse Width
t
19
20 ns
1
Maximum SCLK frequency is 50 MHz at V
DD
= 4.5 V to 5.5 V. Guaranteed by design and characterization; not production tested.
2
Daisy-chain mode only.
3
Measured with the load circuit of Figure 2. t
15
determines the maximum SCLK frequency in daisy-chain mode.
Circuit and Timing Diagrams
2mA I
OL
2mA I
OH
V
OH
(MIN) + V
OL
(MAX)
2
T
O OUTPUT
PIN
C
L
50pF
06844-002
Figure 2. Load Circuit for Digital Output (SDO) Timing Specifications