Datasheet

AD5025/AD5045/AD5065
Rev. 0 | Page 14 of 28
CH1 50mV CH2 5V M4µs A CH2 1.2V
T 8.6%
CH1 200mV p-p
06844-054
V
OUT
SCLK
Figure 36. Glitch Upon Entering Power-Down (1 kΩ to GND) from Zero Scale,
5 kΩ/200 pF Load
CH1 20mV CH2 5V M4µs A CH2 1.2V
T 8.6%
CH1 129mV p-p
06844-055
V
OUT
SCLK
Figure 37. Glitch Upon Exiting Power-Down (1 kΩ to GND) to Zero Scale, No
Load
CH1 20mV CH2 5V M4µs A CH2 1.2V
T 8.6%
CH1 170mV p-p
0
6844-056
V
OUT
SCLK
Figure 38. Glitch Upon Exiting Power-Down (1 kΩ to GND) to Zero Scale,
5 kΩ/200 pF Load
06844-068
CH1 5.00V CH2 1V M1µs A CH1 2.5V
2
1
VOUT
PDL
Figure 39.
PDL
Activation Time