Datasheet

AD5025/AD5045/AD5065
Rev. 0 | Page 13 of 28
24
20
14
8
4
01 5 7 10
SETTLING TIME (μs)
CAPACITANCE (nF)
6
10
12
22
18
16
3924
6
8
V
DD
= 5V, V
REF
= 3.0V
T
A
= 25°C
06844-047
Figure 30. Settling Time vs. Capacitive Load
CH1 5V CH2 2V M2µs A CH1 2.5V
2
1
T 11%
0
6844-048
V
OUT
CLR
Figure 31. Hardware
CLR
10
0
–10
–20
–60
10 100 1000 10000
ATTENUATION (dB)
FREQUENCY (kHz)
–30
–40
–50
CH A
CH B
CH C
CH D
3dB POINT
06844-049
Figure 32. Multiplying Bandwidth
0.0010
0.0008
0.0006
0.0004
0.0002
0
–0.0002
–0.0004
–0.0006
–0.0008
–25 –20 –15 –10 –5 0 5 10 15 20 25 30
ΔVOLTAGE (V)
CURRENT (mA)
CODE = MIDSCALE
V
DD
= 5V, V
REF
= 4.096V
V
DD
= 5.5V
06844-051
Figure 33. Typical Output Load Regulation
0.10
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
–25 –20 –15 –10 –5 0 5 10 15 20 25 30
ΔV
OUT
(V)
I
OUT
(mA)
CODE = MIDSCALE
V
DD
= 5V, V
REF
= 4.096V
06844-052
Figure 34. Typical Current Limiting Plot
CH1 50mV CH2 5V M4µs A CH2 1.2V
T 8.6%
CH1 295mV p-p
06844-053
V
OUT
SCLK
Figure 35. Glitch Upon Entering Power-Down (1 kΩ to GND) from Zero Scale,
No Load