Datasheet

Data Sheet AD5024/AD5044/AD5064
Rev. F | Page 5 of 28
TIMING CHARACTERISTICS
All input signals are specified with t
R
= t
F
= 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2. See Figure 4 and
Figure 5. V
DD
= 4.5 V to 5.5 V. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 4.
Parameter
1
Symbol Min Typ Max Unit
SCLK Cycle Time t
1
20 ns
SCLK High Time t
2
10 ns
SCLK Low Time t
3
10 ns
SYNC
to SCLK Falling Edge Setup Time t
4
17 ns
Data Setup Time
t
5
5
ns
Data Hold Time t
6
5 ns
SCLK Falling Edge to
SYNC
Rising Edge t
7
5 30 ns
Minimum
SYNC
High Time (Single Channel Update) t
8
3 µs
Minimum
SYNC
High Time (All Channel Update) t
8
8 µs
SYNC
Rising Edge to SCLK Fall Ignore t
9
17 ns
LDAC
Pulse Width Low t
10
20 ns
SCLK Falling Edge to
LDAC
Rising Edge t
11
20 ns
CLR
Minimum Pulse Width Low t
12
10 ns
SCLK Falling Edge to
LDAC
Falling Edge t
13
10 ns
CLR
Pulse Activation Time t
14
10.6 µs
SCLK Rising Edge to SDO Valid t
15
2, 3
22 ns
SCLK Falling Edge to
SYNC
Rising Edge t
16
2
5 ns
SYNC
Rising Edge to SCLK Rising Edge t
17
2
8 ns
SYNC
Rising Edge to
LDAC
/
CLR
Falling Edge (Single Channel Update) t
18
2
2 µs
SYNC
Rising Edge to
LDAC
/
CLR
Falling Edge (All Channel Update) t
18
2
8 µs
Power-up Time
4
4.5
µs
1
Maximum SCLK frequency is 50 MHz at V
DD
= 4.5 V to 5.5 V. Guaranteed by design and characterization; not production tested.
2
Daisy-chain mode only.
3
Measured with the load circuit of Figure 3. t
15
determines the maximum SCLK frequency in daisy-chain mode. AD5064-1 only.
4
Time to exit power-down mode to normal mode of AD5024/AD5044/AD5064/AD5064-1, 32
nd
clock edge to 90% of DAC midscale value, with output unloaded.
Circuit and Timing Diagrams
2mA I
OL
2mA I
OH
TO OUTPUT
PIN
C
L
50pF
06803-002
2
V
OH
(MIN) + V
OL
(MAX)
Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications