Datasheet

Data Sheet AD5024/AD5044/AD5064
Rev. F | Page 15 of 28
10
0
–10
–20
–60
10 100 1000 10000
06803-049
ATTENUATION (dB)
FREQUENCY (kHz)
–30
–40
–50
CH A
CH B
CH C
CH D
3dB POINT
Figure 38. Multiplying Bandwidth
5.0
4.0
3.0
2.0
0
06803-050
OUTPUT VOLTAGE (V)
TIME (µs)
1.0
4.5
3.5
2.5
1.5
0.5
V
DD
= 5V, V
REF
= 4.096V
T
A
= 25°C
1/4 SCALE TO 3/4 SCALE
3/4 SCALE TO 1/4 SCALE
OUTPUT LOADED WITH 5kΩ
AND 200pF TO GND
0 2 4 6 8 10 12 14
Figure 39. Typical Output Slew Rate
0.0010
0.0008
0.0006
0.0004
0.0002
0
–0.0002
–0.0004
–0.0006
–0.0008
–25 –20 –15 –10 –5 0 5 10 15 20 25 30
06803-051
∆VOLTAGE (V)
CURRENT (mA)
CODE = MIDSCALE
V
DD
= 5V, V
REF
= 4.096V
Figure 40. Typical Output Load Regulation
0.10
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
–25 –20 –15 –10 –5 0 5 10 15 20 25 30
06803-052
∆V
OUT
(V)
I
OUT
(mA)
CODE = MIDSCALE
V
DD
= 5V, V
REF
= 4.096V
Figure 41. Typical Current Limiting Plot
06803-053
CH1 50mV CH2 5V M4µs A CH2 1.2V
T 8.6%
DAC A 295mV p-p
T
A
= 25°C
V
DD
= 5V, V
REF
= 4.096V
Figure 42. Glitch Upon Entering Power-Down (1 kΩ to GND) from Zero Scale,
No Load
06803-054
CH1 50mV CH2 5V M4µs A CH2 1.2V
T 8.6%
DAC A 200mV p-p
T
A
= 25°C
V
DD
= 5V, V
REF
= 4.096V
SCLK
Figure 43. Glitch Upon Entering Power-Down (1 kΩ to GND) from Zero Scale,
5 kΩ/200 pF Load