Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - DA converter (DAC) TSSOP 14

Fully Accurate, 12-/14-/16-Bit V

OUT

nanoDAC, Quad,

SPI Interface, 4.5 V to 5.5 V in TSSOP

Data Sheet

AD5024/AD5044/AD5064

Rev. F Document Feedback

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FEATURES

Low power quad 12-/14-/16-bit DAC, ±1 LSB INL

Pin compatible and performance upgrade to AD5666

Individual and common voltage reference pin options

Rail-to-rail operation

4.5 V to 5.5 V power supply

Power-on reset to zero scale or midscale

3 power-down functions and per-channel power-down

Hardware

LDAC

with software

LDAC

override function

CLR

function to programmable code

SDO daisy-chaining option

14-/16-lead TSSOP

Internal reference buffer and internal output amplifier

APPLICATIONS

Process control

Data acquisition systems

Portable battery-powered instruments

Digital gain and offset adjustment

Programmable voltage and current sources

Programmable attenuators

FUNCTIONAL BLOCK DIAGRAMS

06803-064

INTERFACE

LOGIC AND

SHIFT

INPUT

DIN

SDO

LDAC

GND

LDAC

REFIN

SYNC

SCLK

AD5064-1

CLR

OUT

DAC

DAC A

BUFFER

INPUT

DAC

DAC B

BUFFER

INPUT

DAC

DAC C

BUFFER

INPUT

DAC

DAC D

BUFFER

POR

POWER-DOWN

LOGIC

POWER-ON

RESET

Figure 1. AD5064-1 Functional Equivalent and Pin Compatible with AD5666

INTERFACE

LOGIC AND

SHIFT

INPUT

DIN

LDAC

GND

LDAC

REF

SYNC

SCLK

AD5024/

AD5044/

AD5064

CLR

OUT

DAC

DAC A

BUFFER

INPUT

DAC

DAC B

BUFFER

INPUT

DAC

DAC C

BUFFER

INPUT

DAC

DAC D

BUFFER

REF

C V

REF

POR

POWER-DOWN

LOGIC

POWER-ON

RESET

06803-001

Figure 2. AD5024/AD5044/AD5064 with Individual Reference Pins

GENERAL DESCRIPTION

The AD5024/AD5044/AD5064/AD5064-1 are low power, quad

12-/14-/16-bit buffered voltage output nanoDAC® converters

that offer relative accuracy specifications of 1 LSB INL and 1 LSB

DNL with the AD5024/AD5044/AD5064 individual reference

pin and the AD5064-1 common reference pin options. The

AD5024/AD5044/AD5064/AD5064-1 can operate from a single

4.5 V to 5.5 V supply. The AD5024/AD5044/AD5064/AD5064-1

also offer a differential accuracy specification of ±1 LSB. The

parts use a versatile 3-wire, low power Schmitt trigger serial

interface that operates at clock rates up to 50 MHz and is compati-

ble with standard SPI, QSPI™, MICROWIRE™, and DSP interface

standards. Integrated reference buffers and output amplifiers are

also provided on-chip. The AD5024/AD5044/AD5064/AD5064-1

incorporate a power-on reset circuit that ensures the DAC

output powers up to zero scale or midscale and remains there

until a valid write takes place to the device. The AD5024/AD5044/

AD5064/AD5064-1 contain a power-down feature that reduces

the current consumption of the device to typically 400 nA at 5 V

and provides software selectable output loads while in power-

down mode. Total unadjusted error for the parts is <2 mV.

PRODUCT HIGHLIGHTS

1. Quad channel available in 14-/16-lead TSSOP packages.

2. 16-bit accurate, 1 LSB INL.

3. High speed serial interface with clock speeds up to 50 MHz.

4. Reset to known output voltage (zero scale or midscale).

Table 1. Related Devices

Part No. Description

AD5666 Quad,16-bit buffered DAC,

16 LSB INL, TSSOP

AD5025/AD5045/AD5065 Dual, 16-bit buffered DACs,

1 LSB INL, TSSOP

AD5062, AD5063 16-bit nanoDAC, 1 LSB INL, SOT-23,

MSOP

AD5061 16-bit nanoDAC, 4 LSB INL, SOT-23

AD5040/AD5060

14-/16-bit

nano

DAC, 1 LSB INL,

SOT-23

Summary of content (28 pages)

PAGE 1
Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad, SPI Interface, 4.5 V to 5.5 V in TSSOP Data Sheet AD5024/AD5044/AD5064 FEATURES FUNCTIONAL BLOCK DIAGRAMS VREFIN VDD AD5064-1 LDAC INTERFACE LOGIC AND SHIFT REGISTER SYNC DIN DAC REGISTER INPUT REGISTER DAC REGISTER DAC B INPUT REGISTER DAC REGISTER DAC C INPUT REGISTER DAC REGISTER DAC D VOUTA DAC A BUFFER VOUTB BUFFER VOUTC BUFFER VOUTD SDO LDAC CLR POWER-ON RESET POWER-DOWN LOGIC POR GND Figure 1.
PAGE 2
AD5024/AD5044/AD5064 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Output Amplifier ........................................................................ 19 Applications ....................................................................................... 1 Serial Interface ............................................................................ 19 Functional Block Diagrams ...............................
PAGE 3
Data Sheet AD5024/AD5044/AD5064 SPECIFICATIONS VDD = 4.5 V to 5.5 V, RL = 5 kΩ to GND, CL = 200 pF to GND, 2.5 V ≤ VREFIN ≤ VDD, unless otherwise specified. All specifications TMIN to TMAX, unless otherwise noted. Table 2.
PAGE 4
AD5024/AD5044/AD5064 Parameter LOGIC OUTPUTS (SDO) 9 Output Low Voltage, VOL Output High Voltage, VOH High Impedance Leakage Current High Impedance Output Capacitance6 POWER REQUIREMENTS VDD IDD 10 Normal Mode All Power-Down Modes 11 Min Data Sheet B Grade 1 Typ Max A Grade1, 2 Typ Min 0.4 VDD − 1 Max Unit Conditions/Comments 0.4 V ISINK = 2 mA ISOURCE = 2 mA ±1 μA VDD − 1 ±0.002 ±1 ±0.002 7 7 4.5 5.5 4 0.4 4.5 6 2 30 4 0.4 pF 5.
PAGE 5
Data Sheet AD5024/AD5044/AD5064 TIMING CHARACTERISTICS All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4 and Figure 5. VDD = 4.5 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted. Table 4.
PAGE 6
AD5024/AD5044/AD5064 Data Sheet t1 t9 SCLK t8 t2 t3 t4 t7 SYNC t5 DIN t6 DB31 DB0 t13 t10 LDAC1 t11 LDAC2 t12 CLR 06803-003 t14 VOUT 1ASYNCHRONOUS LDAC UPDATE MODE. 2SYNCHRONOUS LDAC UPDATE MODE. Figure 4. Serial Write Operation SCLK 32 t8 64 t17 t4 t16 SYNC t5 DIN t6 DB31 DB0 DB0 DB31 INPUT WORD FOR DAC N + 1 INPUT WORD FOR DAC N t15 DB31 SDO UNDEFINED DB0 INPUT WORD FOR DAC N t18 t10 LDAC1 CLR 1IF IN DAISY-CHAIN MODE, LDAC MUST BE USED ASYNCHRONOUSLY.
PAGE 7
Data Sheet AD5024/AD5044/AD5064 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Parameter VDD to GND Digital Input Voltage to GND VOUT to GND VREF to GND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature (TJ MAX) TSSOP Package Power Dissipation θJA Thermal Impedance Reflow Soldering Peak Temperature Pb-Free Rating −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.
PAGE 8
AD5024/AD5044/AD5064 Data Sheet LDAC 1 14 SCLK SYNC 2 13 DIN VDD 3 12 GND VOUTA 4 AD5064-1 11 VOUTB TOP VIEW (Not to Scale) 10 VOUTD VOUTC 5 POR 6 9 CLR VREFIN 7 8 SDO 06803-065 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 6. 14-Lead TSSOP (RU-14) Table 6. Pin Function Descriptions Pin No.
PAGE 9
Data Sheet AD5024/AD5044/AD5064 LDAC 1 16 SCLK SYNC 2 15 DIN 3 4 VREF A 5 VOUTA 6 VOUTC 7 POR 8 AD5024/ AD5044/ AD5064 TOP VIEW (Not to Scale) 14 GND 13 VOUTB 12 VOUTD 11 VREF D 10 CLR 9 VREF C 06803-005 VDD VREF B Figure 7. 16-Lead TSSOP (RU-16) Pin Configuration Table 7. Pin Function Descriptions Pin No.
PAGE 10
AD5024/AD5044/AD5064 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0 –0.2 0 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –1.0 512 16,640 32,768 48,896 VDD = 5V VREF = 4.096V TA = 25°C 06803-022 DNL (LSB) VDD = 5V = 4.096V V 0.8 T REF A = 25°C 06803-019 INL (LSB) 1.0 –0.8 –1.0 512 65,024 16,640 DAC CODE 48,896 65,024 Figure 11. AD5064/AD5064-1 DNL Figure 8. AD5064/AD5064-1 INL 1.0 1.0 VDD = 5V 0.8 VREF = 4.096V TA = 25°C 0.6 0.6 0.4 0.2 0.2 0 –0.
PAGE 11
Data Sheet AD5024/AD5044/AD5064 0.20 1.2 VDD = 5V VREF = 4.096V TA = 25°C 0.15 1.0 0.8 0.10 0.6 0.4 TUE (mV) 0.05 TUE (mV) TA = 25°C 0 –0.05 0.2 MAX TUE @ VDD = 5.5V 0 MIN TUE @ VDD = 5.5V –0.2 –0.15 –0.8 06803-025 –0.6 –0.20 512 16,640 32,768 48,896 06803-028 –0.4 –0.10 –1.0 –1.2 2.0 65,024 2.5 3.0 DAC CODE Figure 14. Total Unadjusted Error (TUE) 5.0 5.5 0.010 GAIN ERROR (%FSR) DAC A MAX INL ERROR @ VDD = 5.5V 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 –1.
PAGE 12
AD5024/AD5044/AD5064 Data Sheet 10 0.2 VDD = 5.5V VREF = 4.096 TA = 25°C VREF = 4.096V TA = 25°C 8 IDD (mA) ERROR (%FSR) 0.1 GAIN ERROR 0 6 4 FULL-SCALE ERROR –0.1 06803-031 2 4.75 5.00 5.25 0 0 5.50 10,000 20,000 30,000 VDD (V) 40,000 50,000 60,000 06803-034 –0.2 4.50 70,000 DAC CODE Figure 20. Gain Error and Full-Scale Error vs. Supply Voltage Figure 23. Supply Current vs. Code 10 0.12 VDD = 5.5V VREF = 4.096 CODE = MIDSCALE VREF = 4.
PAGE 13
Data Sheet 10 AD5024/AD5044/AD5064 VREF = 4.096V TA = 25°C OUTPUT UNLOADED VDD = 5.5V VREF = 4.096 TA = 25°C VDD 8 IDD (mA) 6 1 DAC A 4 3 06803-040 2 0 1 2 3 4 06803-037 0 5 DIGITAL INPUT VOLTAGE (V) CH1 2V Figure 26. Supply Current vs. Digital Input Voltage CH3 2V M2ms T 20.4% A CH1 2.52V Figure 29. Power-On Reset to Midscale 5.0 CH1 = SCLK 4.5 OUTPUT VOLTAGE (V) 4.0 1 3.5 VDD = 5V, VREF = 4.
PAGE 14
AD5024/AD5044/AD5064 Data Sheet 0 7 VDD = 5V, VREF = 4.096V TA = 25ºC 6 –20 4 VOUT LEVEL (dB) –30 3 2 1 0 –40 –50 –60 –70 –1 –80 06803-043 –2 –3 0 2.5 5.0 7.5 06803-046 GLITCH AMPLITUDE (mV) 5 –4 VDD = 5V, TA = 25ºC DAC LOADED WITH MIDSCALE VREF = 3.0V ± 200mV p-p –10 –90 –100 10.0 5 20 10 TIME (μs) Figure 32. Analog Crosstalk 55 9 10 24 VDD = 5V, VREF = 3.0V 22 TA = 25°C 1/4 SCALE TO 3/4 SCALE WITHIN ±1LSB 20 VDD = 5V, VREF = 4.
PAGE 15
Data Sheet AD5024/AD5044/AD5064 10 0.10 0.08 0 CODE = MIDSCALE VDD = 5V, VREF = 4.096V 0.06 0.04 ∆VOUT (V) –20 –30 0.02 0 –0.02 –0.04 –40 CH A CH B CH C CH D 3dB POINT –0.06 06803-049 –50 –60 10 100 1000 06803-052 ATTENUATION (dB) –10 –0.08 –0.10 –25 10000 –20 –15 –10 FREQUENCY (kHz) –5 0 10 15 20 25 30 Figure 41. Typical Current Limiting Plot Figure 38. Multiplying Bandwidth 5.0 TA = 25°C VDD = 5V, VREF = 4.096V 4.5 DAC A 295mV p-p 4.
PAGE 16
AD5024/AD5044/AD5064 Data Sheet VDD = 5V,VREF = 4.096V TA = 25°C TA = 25°C VDD = 5V, VREF = 4.096V 06803-055 SCLK CH1 20mV CH2 5V M4µs T 8.6% A CH2 06803-056 DAC A 170mV p-p DAC A 129mV p-p SCLK 1.2V CH1 20mV Figure 44. Glitch Upon Exiting Power-Down (1 kΩ to GND) to Zero Scale, No Load CH2 5V M4µs T 8.6% A CH2 1.2V Figure 45. Glitch Upon Exiting Power-Down (1 kΩ to GND) to Zero Scale, 5 kΩ/200 pF Load Rev.
PAGE 17
Data Sheet AD5024/AD5044/AD5064 TERMINOLOGY Relative Accuracy (INL) For the DAC, relative accuracy, or integral nonlinearity (INL), is a measure of the maximum deviation in LSBs from a straight line passing through the endpoints of the DAC transfer function. Figure 8, Figure 9, and Figure 10 show plots of typical INL vs. code. DC Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the supply voltage.
PAGE 18
AD5024/AD5044/AD5064 Data Sheet DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s or vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nanovolt-seconds.
PAGE 19
Data Sheet AD5024/AD5044/AD5064 THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER OUTPUT AMPLIFIER The AD5024/AD5044/AD5064/AD5064-1 are single 12-/14-/ 16-bit, serial input, voltage output DACs with an individual reference pin. The AD5064-1 model (see the Ordering Guide) is a 16-bit, serial input, voltage output DAC that is identical to other AD5064 models but with a single reference pin for all DACs. The parts operate from supply voltages of 4.5 V to 5.5 V.
PAGE 20
AD5024/AD5044/AD5064 Data Sheet DB31 (MSB) X X DB0 (LSB) X X C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X COMMAND BITS 06803-009 DATA BITS ADDRESS BITS Figure 47. AD5024 Shift Register Content DB31 (MSB) X X DB0 (LSB) X X C3 C2 C1 C0 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X COMMAND BITS 06803-008 DATA BITS ADDRESS BITS Figure 48.
PAGE 21
Data Sheet AD5024/AD5044/AD5064 MODES OF OPERATION There are three main modes of operation: standalone mode where a single device is used, daisy-chain mode for a system that contains several DACs, and power-down mode when the supply current falls to 0.4 µA at 5 V. Standalone Mode The write sequence begins by bringing the SYNC line low. Data from the DIN line is clocked into the 32-bit shift register on the falling edge of SCLK.
PAGE 22
AD5024/AD5044/AD5064 Data Sheet The AD5024/AD5044/AD5064/AD5064-1 contain a power-on reset circuit that initializes the registers to their default values and controls the output voltage during power-up. By connecting the POR pin low, the AD5024/AD5044/AD5064/AD5064-1 output powers up to zero scale. Note that this is outside the linear region of the DAC; by connecting the POR pin high, the AD5024/AD5044/AD5064/AD5064-1 output powers up to midscale.
PAGE 23
Data Sheet AD5024/AD5044/AD5064 CLEAR CODE REGISTER Synchronous LDAC: After new data is read, the DAC registers are updated on the falling edge of the 32nd SCLK pulse, provided LDAC is held low. The AD5024/AD5044/AD5064/AD5064-1 have a hardware CLR pin that is an asynchronous clear input. The CLR input is falling edge sensitive.
PAGE 24
AD5024/AD5044/AD5064 Data Sheet POWER SUPPLY BYPASSING AND GROUNDING When accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. The printed circuit board (PCB) containing the AD5024/AD5044/ AD5064/AD5064-1 should have separate analog and digital sections. If the AD5024/AD5044/AD5064/AD5064-1 are in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only.
PAGE 25
Data Sheet AD5024/AD5044/AD5064 AD5024/AD5044/AD5064/AD5064-1 to Blackfin ADSPBF53x Interface Figure 52 shows a serial interface between the AD5024/AD5044/ AD5064/AD5064-1 and the Blackfin® ADSP-BF53x microprocessor. The ADSP-BF53x processor family incorporates two dualchannel synchronous serial ports, SPORT1 and SPORT0, for serial and multiprocessor communications.
PAGE 26
AD5024/AD5044/AD5064 Data Sheet APPLICATIONS INFORMATION Because the supply current required by the AD5024/AD5044/ AD5064/AD5064-1 is extremely low, an alternative option is to use a voltage reference to supply the required voltage to the parts (see Figure 56). This is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5 V (for example, 15 V). The voltage reference outputs a steady supply voltage for the AD5024/AD5044/AD5064/ AD5064-1.
PAGE 27
Data Sheet AD5024/AD5044/AD5064 OUTLINE DIMENSIONS 5.10 5.00 4.90 14 8 4.50 4.40 4.30 6.40 BSC 1 7 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.20 0.09 SEATING PLANE 0.30 0.19 8° 0° 0.75 0.60 0.45 061908-A 1.05 1.00 0.80 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 59. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.65 BSC 0.30 0.
PAGE 28
AD5024/AD5044/AD5064 Data Sheet ORDERING GUIDE Model 1 AD5064ARUZ-1 AD5064ARUZ-1REEL7 AD5064BRUZ-1 AD5064BRUZ-1REEL7 AD5064BRUZ AD5064BRUZ-REEL7 AD5044BRUZ AD5044BRUZ-REEL7 AD5024BRUZ AD5024BRUZ-REEL7 EVAL-AD5064-1EBZ EVAL-AD5064EBZ 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Accuracy ±4 LSB INL ±4 LSB INL ±1 LSB INL ±1 LSB INL ±1 LSB INL ±1 LSB INL ±1 LSB INL ±1 LSB IN