Datasheet

AD5061
Rev. B | Page 13 of 20
0.0010
0.0008
0.0006
0.0004
0.0002
0
–0.0002
–0.0004
–0.0006
–0.0008
–25 –20 –15 –10 –5 0 5 10 15 20 25 30
04762-051
∆ VOLTAGE (V)
CURRENT (mA)
CODE = MIDSCALE
V
DD
= 5V, V
REF
= 4.096V
V
DD
= 3V, V
REF
= 2.5V
V
DD
= 5.5V
V
DD
= 3V
Figure 34. Typical Output Load Regulation
0.10
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
–25 –20 –15 –10 –5 0 5 10 15 20 25 30
04762-063
∆ V
OUT
(V)
I
OUT
(mA)
CODE = MIDSCALE
V
DD
= 5V, V
REF
= 4.096V
V
DD
= 3V, V
REF
= 2.5V
V
DD
= 3V, V
REF
= 2.5V
V
DD
= 5V, V
REF
= 4.096V
Figure 35. Typical Current Limiting Plot
2.1
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
–10µs 9.96µs8µs6µs4µs2µs0–2µs–4µs–6µs–8µs
04762-052
V
DD
= 5.5V
V
REF
= 4.096V
10% TO 90% RISE TIME = 0.688µs
SLEW RATE = 1.16V/µs
DAC
OUTPUT
1.04V
2.04V
Figure 36. Typical Output Slew Rate