Datasheet

AD5040/AD5060
Rev. A | Page 5 of 24
TIMING CHARACTERISTICS
V
DD
= 2.7 V to 5.5 V; all specifications T
MIN
to T
MAX
,
unless otherwise noted.
Table 3.
Parameter Limit
1
Unit Test Conditions/Comments
t
1
2
33 ns min SCLK cycle time
t
2
5 ns min SCLK high time
t
3
3 ns min SCLK low time
t
4
10 ns min
SYNC to SCLK falling edge setup time
t
5
3 ns min Data setup time
t
6
2 ns min Data hold time
t
7
0 ns min
SCLK falling edge to SYNC rising edge
t
8
12 ns min
Minimum SYNC high time
t
9
9 ns min
SYNC rising edge to next SCLK fall ignore
1
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
2
Maximum SCLK frequency is 30 MHz.
t
4
t
3
t
2
t
5
t
7
t
6
D0D1D2D22D23
SYNC
SCLK
04767-002
t
9
t
1
t
8
D23 D22
DIN
Figure 2. AD5060 Timing Diagram