Datasheet
AD5040/AD5060
Rev. A | Page 18 of 24
AD5040/AD5060 to MICROWIRE Interface
AD5040/AD5060 to Blackfin® ADSP-BF53x Interface
Figure 49 shows an interface between the AD5040/AD5060 and
any MICROWIRE-compatible device. Serial data is shifted out
on the falling edge of the serial clock and is clocked into the
AD5040/AD5060 on the rising edge of the SK.
Figure 47 shows a serial interface between the AD5040/
AD5060 and the Blackfin ADSP-53x microprocessor. The
ADSP-BF53x processor family incorporates two dual-channel
synchronous serial ports, SPORT1 and SPORT0, for serial and
multiprocessor communications. Using SPORT0 to connect to
the AD5040/AD5060, the setup for the interface is: DT0PRI
drives the SDIN pin of the AD5040/AD5060, while TSCLK0
drives the SCLK of the part; the
SYNC
is driven from TFS0.
MICROWIRE
1
1
ADDITIONAL PINS OMITTED FOR CLARITY
CS
SK
SO
SYNC
SCLK
DIN
04767-035
AD5040/
AD5060
1
ADSP-BF53x
1
1
ADDITIONAL PINS OMITTED FOR CLARITY
DT0PRI
TSCLK0
TFS0
DIN
SCLK
SYNC
04767-033
AD5040/
AD5060
1
Figure 49. AD5040/AD5060 to MICROWIRE Interface
Figure 47. AD5040/AD5060 to Blackfin® ADSP-BF53x Interface
AD5040/AD5060 to 80C51/80L51 Interface
Figure 48 shows a serial interface between the AD5060/
AD5040 and the 80C51/80L51 microcontroller. The setup
for the interface is: TxD of the 80C51/80L51 drives SCLK of
the AD5040/AD5060 while RxD drives the serial data line
of the part. The
SYNC
signal is again derived from a bit-
programmable pin on the port. In this case, Port Line P3.3 is
used. When data is to be transmitted to the AD5040, P3.3 is
taken low. The 80C51/80L51 transmits data only in 8-bit bytes;
thus only 8 falling clock edges occur in the transmit cycle. To
load data to the DAC, P3.3 is left low after the first eight bits are
transmitted, and a second write cycle is initiated to transmit the
second byte of data. P3.3 is taken high following the completion
of this cycle. The 80C51/80L51 outputs the serial data in a
format which has the LSB first. The AD5040/AD5060 require
data to be received with the MSB as the first bit. The
80C51/80L51 transmit routine should take this into account.
80C51/80L51
1
1
ADDITIONAL PINS OMITTED FOR CLARITY
P3.3
TxD
RxD
SYNC
SCLK
DIN
04767-034
AD5040/
AD5060
1
Figure 48. AD5040/AD5060 to 80C51/80L51 Interface