Datasheet

AD5040/AD5060
Rev. A | Page 13 of 24
04767-050
CH3 2.00V CH2 50mV M1.00ms CH3 1.36V
2
C2
30mV p-p
C3
4.96V p-p
C3 FALL
∞s
NO VALID
EDGE
C3 RISE
946.2μs
3
T
T
2.1
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
–10
μ s 9.96 μ s8 μ s6 μ s4 μ s2 μ s0–2 μ s–4 μ s–6 μ s–8 μ s
04767-052
V
DD
= 5.5V
V
REF
= 4.096V
10% TO 90% RISE TIME = 0.688
μ s
SLEW RATE = 1.16V/
μ s
DAC
OUTPUT
1.04V
2.04V
Figure 34. Glitch upon Exiting Hardware Power-Down to Zero Scale
Figure 37. Typical Output Slew Rate
0.0010
0.0008
0.0006
0.0004
0.0002
0
–0.0002
–0.0004
–0.0006
–0.0008
–25 –20 –15 –10 –5 0 5 10 15 20 25 30
04767-051
Δ
VOLTAGE (V)
CURRENT (mA)
CODE = MID-SCALE
V
DD
= 5V, V
REF
= 4.096V
V
DD
= 3V, V
REF
= 2.5V
V
DD
= 5.5V
V
DD
= 3V
16
14
0
2
4
6
8
10
12
0.83 MORE0.910.900.890.880.870.860.850.84
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FREQUENCY
BIN
Figure 35. Typical Output Load Regulation
Figure 38. I
DD
Histogram V
DD
= 3.0 V
0.10
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
–25 –20 –15 –10 –5 0 5 10 15 20 25 30
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Δ
V
OUT
(V)
I
OUT
(mA)
CODE = MIDSCALE
V
DD
= 5V, V
REF
= 4.096V
V
DD
= 3V, V
REF
= 2.5V
V
DD
= 3V, V
REF
= 2.5V
V
DD
= 5V, V
REF
= 4.096V
14
0
2
4
6
8
10
12
1.00 1.01 1.02 1.03 1.04 1.05 1.06 1.07 1.08 1.09 1.10 1.11MORE
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FREQUENCY
BIN
Figure 36. Typical Current Limiting Plot
Figure 39. I
DD
Histogram V
DD
= 5.0 V