Datasheet

AD421
–3–
REV. C
TIMING CHARACTERISTICS
1, 2, 3
Parameter (B Versions) Units Conditions/Comments
t
CK
100 ns min Data Clock Period
t
CL
50 ns min Data Clock Low Time
t
CH
50 ns min Data Clock High Time
t
DW
30 ns min Data Stable Width
t
DS
30 ns min Data Setup Time
t
DH
0 ns min Data Hold Time
t
LD
50 ns min Latch Delay Time
t
LL
50 ns min Latch Low Time
t
LH
50 ns min Latch High Time
NOTES
1
Guaranteed by characterization at initial product release, not production tested.
2
See Figures 1 and 2.
3
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
CC
) and timed from a voltage level of (V
IN
+ V
IL
)/2; tr and tf should not exceed 1 µs on any digital
input.
Specifications subject to change without notice.
WORD "N" WORD "N +1"
10 11 11111
1
00 00 00 1 00 1
CLOCK
DATA
LATCH
B15
(MSB)
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
B15 B14
B13
B12
(LSB)
Figure 1. Serial Interface Waveforms (Normal Data Load)
CLOCK
DATA
LATCH
t
CK
t
CL
t
CH
t
DS
t
DH
t
DW
t
LD
t
LL
t
LH
Figure 2. Serial Interface Timing Diagram
(V
CC
= +3 V to +5 V, T
A
= T
MIN
to T
MAX
unless otherwise noted)