Datasheet

AD2S90
REV. D
–3–
AD2S90
Parameter Min Max Units Test Conditions/Notes
t
DIR
200 ns DIR to CLKOUT Positive Edge
t
CLK
250 400 ns CLKOUT Pulsewidth
t
ABN
250 ns CLKOUT Negative Edge to A, B and NM Transition
Parameter AD2S90 Units Test Conditions/Notes
t
1
150 ns max CS to DATA Enable
t
2
1
600 ns min CS to 1st SCLK Negative Edge
t
3
250 ns min SCLK Low Pulse
t
4
250 ns min SCLK High Pulse
t
5
100 ns max SCLK Negative Edge to DATA Valid
t
6
600 ns min CS High Pulsewidth
t
7
150 ns max CS High to DATA High Z (Bus Relinquish)
NOTE
1
SCLK can only be applied after t
2
has elapsed.
(V
DD
= +5 V ⴞ 5%, V
SS
= –5 V ⴞ 5%, AGND = DGND = 0 V, T
A
= –40ⴗC to +85ⴗC unless
otherwise noted)
TIMING CHARACTERISTICS
1, 2
LSBMSB
t
3
t
4
t
5
t
1
t
7
t
6
t*
t
2
*THE MINIMUM ACCESS TIME: USER DEPENDENT
CSB
SCLK
DATA
Figure 1. Serial Interface
NOTES
1
Timing data are not 100% production tested. Sample tested at +25°C only to ensure conformance to data sheet limits. Logic output timing tests carried out using
10 pF, 100 kΩ load.
2
Capacitance of data pin in high impedance state = 15 pF.
A
B
908
1808
NM
NUMBER OF DEGREES REFERS TO WIDTH RELATIVE TO "A" CYCLE
3608
Figure 2. Incremental Encoder
CLKOUT
A, B, NM
DIR
COUNTER IS CLOCKED
ON THIS EDGE
t
DIR
t
ABN
t
CLK
Figure 3. DIR/CLKOUT/A, B and NM Timing