Datasheet

Parameter Conditions Min Typ Max Unit
COMPLEMENT Internally Pulled High via 100 kΩ
to +V
S
. Logic LO to Activate;
No Connect for Normal Operation
DATA LOAD
Sense Internally Pulled High via 100 kΩ 150 300 ns
to +V
S
. Logic LO Allows
Data to be Loaded into the
Counters from the Data Lines
BUSY
6, 7
Sense Logic HI When Position O/P Changing
Width 150 350 ns
Load Use Additional Pull-Up (See Figure 2) 1 LSTTL
DIRECTION
6
Sense Logic HI Counting Up
Logic LO Counting Down
Max Load 3 LSTTL
RIPPLE CLOCK
6
Sense Logic HI
All 1s to All 0s
All 0s to All 1s
Width Dependent on Input Velocity 300 ns
Reset Before Next Busy
Load 3 LSTTL
DIGITAL INPUTS
Input High Voltage, V
IH
INHIBIT, ENABLE 2.0 V
DB1–DB16, Byte Select
±V
S
= ±11.4 V, V
L
= 5.0 V
Input Low Voltage, V
IL
INHIBIT, ENABLE 0.8 V
DB1–DB16, Byte Select
±V
S
= ±12.6 V, V
L
= 5.0 V
DIGITAL INPUTS
Input High Current, I
IH
INHIBIT, ENABLE  100 µA
DB1–DB16
±V
S
= ±12.6 V, V
L
= 5.5 V
Input Low Current, I
IL
INHIBIT, ENABLE  100 µA
DB1–DB16, Byte Select
±V
S
= ±12.6 V, V
L
= 5.5 V
DIGITAL INPUTS
Low Voltage, V
IL
ENABLE = HI 1.0 V
SC1, SC2, DATA LOAD
±V
S
= ±12.0 V, V
L
= 5.0 V
Low Current, I
IL
ENABLE = HI –400 µA
SC1, SC2, DATA LOAD
±V
S
= ±12.0 V, V
L
= 5.0 V
DIGITAL OUTPUTS
High Voltage, V
OH
DB1–DB16 2.4 V
RIPPLE CLK, DIR
±V
S
= ±12.0 V, V
L
= 4.5 V
I
OH
= 100 µA
Low Voltage, V
OL
DB1–DB16 0.4 V
RIPPLE CLK, DIR
±V
S
= ±12.0 V, V
L
= 5.5 V
I
OL
= 1.2 mA
NOTES
1
Angular accuracy is not guaranteed <50 Hz reference frequency.
2
Linearity derates from 500 kHz–1000 kHz @ 0.0017%/kHz.
3
Refer to Definition of Linearity, “The AD2S83 as a Silicon Tachogenerator.”
4
Worst case reversion error at temperature extremes.
5
Velocity output offset dependent on value for R6.
6
Refer to timing diagram.
7
Busy pulse guaranteed up to a VCO rate of 900 kHz.
All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test.
Specifications subject to change without notice.
AD2S83
–3–
REV. E