Datasheet

AD2S1210
Rev. A | Page 7 of 36
Parameter Description Limit at T
MIN
, T
MAX
Unit
t
29
Delay WR
/FSYNC rising edge to SDO high-Z
15 ns min
t
30
Delay from SAMPLE
before WR/FSYNC falling edge
6 × t
CK
+ 20 ns ns min
t
31
Delay CS
falling edge to WR/FSYNC falling edge in normal mode
2 ns min
t
32
A0 and A1 setup time before WR
/FSYNC falling edge
2 ns min
t
33
A0 and A1 hold time after WR
/FSYNC falling edge
2
In normal mode, A0 = 0, A1 = 0/1 24 × t
CK
+ 5 ns ns min
In configuration mode, A0 = 1, A1 = 1 8 × t
CK
+ 5 ns ns min
t
34
Delay WR
/FSYNC rising edge to WR/FSYNC falling edge
10 ns min
f
SCLK
Frequency of SCLK input
V
DRIVE
= 4.5 V to 5.25 V 20 MHz
V
DRIVE
= 2.7 V to 3.6 V 25 MHz
V
DRIVE
= 2.3 V to 2.7 V 15 MHz
1
Temperature ranges are as follows: A, B grades: –40°C to +85°C; C, D grades: –40°C to +125°C.
2
A0 and A1 should remain constant for the duration of the serial readback. This may require 24 clock periods to read back the 8-bit fault information in addition to the
16 bits of position/velocity data. If the fault information is not required, A0/A1 may be released following 16 clock cycles.