Datasheet
AD2S1210
Rev. A | Page 19 of 36
48 47
REFOUT
46
REFBYP
45
COS
44
COSLO
43
AV
DD
42
SINLO
41
SIN
40
AGND
39
EXC
38
EXC
37
35
34
33
30
31
32
36
29
28
27
25
26
2
3
4
7
CLKIN
6
DV
DD
5
DGND
1
8
XTALOUT
9
10
12
11
13
14 15
16
17
18
V
DRIVE
19
DGND
20
21
22 23 24
AD2S1210
07467-025
20pF 20pF
8.192
MHZ
4.7µF10nF
5V
5V
10nF 10µF
4.7µF 10nF
BUFFER
CIRCUIT
BUFFER
CIRCUIT
S2 R2
S4 S3 S1 R1
10nF
V
DRIVE
4.7µF
Figure 27 shows a suggested buffer circuit. Capacitor C1 may be
used in parallel with Resistor R2 to filter out any noise that may
exist on the EXC and
EXC
outputs. Care should be taken when
selecting the cutoff frequency of this filter to ensure that phase
shifts of the carrier caused by the filter do not exceed the phase
lock range of the AD2S1210.
The gain of the circuit is
))1/(1()/( ωC1R2R1R2GainCarrier
×
×
+×
−
=
(7)
and
INREF
OUT
V
C1R2R1
R2
R1
R2
VV
⎟
⎠
⎞
⎜
⎝
⎛
××+
×
⎟
⎠
⎞
⎜
⎝
⎛
−
⎟
⎠
⎞
⎜
⎝
⎛
⎟
⎠
⎞
⎜
⎝
⎛
+×=
ω
1
1
1 (8)
where:
ω is the radian frequency of the applied signal.
V
REF
, a dc voltage, is set so that V
OUT
is always a positive value,
eliminating the need for a negative supply.
C1
R2
R1
12V
12V
5V
EXC/EXC
(V
IN
)
(V
REF
)
V
OUT
07467-026
AD8662
Figure 26. Connecting the AD2S1210 to a Resolver
In this recommended configuration, the converter introduces a
V
REF
/2 offset in the SIN, SINLO, COS, and COSLO signal outputs
from the resolver. The sine and cosine signals can each be
connected to a different potential relative to ground if the sine
and cosine signals adhere to the recommended specifications.
Note that because the EXC and
EXC
outputs are differential,
there is an inherent gain of 2×.
Figure 27. Buffer Circuit
A separate screened twisted pair cable is recommended for the
analog input pins, SIN, SINLO, COS, and COSLO. The screens
should terminate to either REFOUT or AGND.