Datasheet

AD2S1200
Rev. 0 | Page 13 of 24
04406-0-007
t
3
t
6
t
7
t
CK
CLKIN
DATA
DON'T CARE
VELPOS
t
2
SAMPLE
CS
RD
RDVEL
t
1
t
1
t
3
t
5
t
4
t
5
t
4
t
7
t
6
Figure 7. Parallel Port Read Timing
Table 5. Parallel Port Timing
Parameter Description Min Typ Max
t
CK
Clock Period (= 1/8.192 MHz) ~122 ns
t
1
SAMPLE
Pulse Width
2 × t
CK
+ 20 ns
t
2
Delay from SAMPLE
before RD/CS Low
6 × t
CK
+ 20 ns
t
3
RD
Pulse Width
18 ns
t
4
Set Time RDVEL
before RD/CS Low
5 ns
t
5
Hold Time RDVEL
after RD/CS Low
7 ns
t
6
Enable Delay RD
/CS Low to Data Valid
12 ns
t
7
Disable Delay RD
/CS Low to Data High Z
18 ns