Datasheet

REV. 0–16–
AD1955
DSD_DATA
DSD_BCLK
DSD_DATA
DSD_BCLK
DSD_PHASE_0
DSD_PHASE_1
DSD_PHASE_2
DSD_PHASE_3
D0 D1
D0
D0
NORMAL
MODE
PHASE
MOD
MODE
Figure 3. DSD Modes
DSD_PHASE
DSD_SCLK
DSD_LDATA, DSD_RDATA
t
DPHS
t
DSKP
t
DSKH
t
DSKL
t
DSDS
t
DSDH
Figure 4. DSD Serial Port Timing
CLATCH
CCLK
CDATA
D15 D14 D0
t
CLKL
t
CLKH
t
CDS
t
CDH
t
CLATCHH
Figure 5. Serial Control Port Timing