Datasheet

REV. 0–14–
AD1955
For example, with the stereo circuits given in Figures 7 through
10, this gives:
12 0 2 80 3 24 2 80 2 00 1 98. – .. .. .VV mA VK k
[]
+
()
[]
=Ω
A 2.00 kΩ resistor is used.
The supply used should be as quiet as possible.
Serial Control Port
The AD1955 has an SPI compatible control port to permit pro-
gramming the internal control registers. The SPI control port is
a 3-wire serial port. Its format is similar to the Motorola SPI
format except that the input data-word is 16 bits wide. The serial
bit clock may be completely asynchronous to the sample rate of the
DAC. The following figure shows the format of the SPI signal
Note that the CCLK may be continuous or a 16-clock burst.
SPI REGISTER DEFINITIONS
Table I. DAC Control Register 0
Bit Description Value Definition
15 Power-Down 0 Operation
1Powered Down
14 Mute 0 Not Muted
1 Muted
13:12 Data Format 00 PCM
01 External DF
10 SACD Slave
11 SACD Master
11:10 Output Format 00 Stereo
01 Not Allowed
10 Mono Left
11 Mono Right
9:8 PCM Sample Rate 00 48 kHz
01 96 kHz
10 192 kHz
11 Reserved
7:6 De-Emphasis Curve 00 None
Select 01 44.1 kHz
10 32 kHz
11 48 kHz
5:4 PCM/EF Serial Data 00 I
2
S
Format 01 Right-Justified
10 DSP
11 Left-Justified
3:2 PCM/EF Serial Data 00 24 bits
Width 01 20 bits
10 18 bits
11 16 bits
1:0 SPI Register Address 00
Default = 0
Table II. DAC Control Register 1
Bit Description Value Definition
10:9 MCLK Mode 00 256  f
S
01 512  f
S
10 768  f
S
11 Reserved
8Zero Flag Polarity 0 Active High
1Active Low
7SACD Bit Rate 0 64  f
S
1 128  f
S
6SACD Mode 0 Normal
1 Phase Mode
5:4 SACD Phase Select 00 Phase 0
01 Phase 1
10 Phase 2
11 Phase 3
3SACD Bit Inversion 0 Normal
1 Inverted
2SACD MCLK to 0 Rising Edge
BCLK Phase 1 Falling Edge
1:0 SPI Register Address 01
Default = 0
Table III. DAC Volume Registers
Bit Description Value Definition
14-Bit
15:2 Volume Unsigned
1:0 SPI Register Address 10 Left Volume
11 Right Volume
Default = Full Volume