Datasheet

AD1940/AD1941
Rev. B | Page 7 of 36
DIGITAL TIMING DIAGRAMS
BCLK_IN
LRCLK_IN
SDATA_INX
LEFT-JUSTIFIED
MODE
LSB
SDATA_INX
I
2
S-JUSTIFIED
MODE
SDATA_INX
RIGHT-JUSTIFIED
MODE
t
BIH
MSB
MSB-1
MSB
MSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
t
LIS
t
SIS
t
SIH
t
SIH
t
SIS
t
SIS
t
SIH
t
SIS
t
SIH
t
LIH
t
BIL
04607-0-013
Figure 2. Serial Input Port Timing
BCLK_OUTX
LRCLK_OUTX
SDATA_OUTX
LEFT-JUSTIFIED
MODE
LSB
SDATA_OUTX
I
2
S-JUSTIFIED
MODE
SDATA_OUTX
RIGHT-JUSTIFIED
MODE
t
BIH
MSB
MSB-1
MSB
MSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
t
LOS
t
SDDS
t
SDDM
t
SDDS
t
SDDM
t
SDDS
t
SDDM
t
LCH
t
TS
t
BIL
04607-0-014
Figure 3. Serial Output Port Timing