Datasheet

AD1940/AD1941
Rev. B | Page 4 of 36
DIGITAL TIMING
VDD = 2.25 to 2.75 V. Specifications measured across –40°C to 125°C.
Table 4. Digital Timing
1
Parameter Mnemonic Comments Min Max Unit
MASTER CLOCK, SERIAL DATA PORTS, RESET
MCLK Period t
MP
512 f
S
mode 36 244 ns
MCLK Period t
MP
384 f
S
mode 48 366 ns
MCLK Period t
MP
256 f
S
mode 73 488 ns
MCLK Period t
MP
64 f
S
mode 291 1953 ns
MCLK Period t
MP
Bypass mode 12 ns
MCLK Duty Cycle t
MDC
Bypass mode 40 60 %
BCLK_IN LO Pulse Width t
BIL
4 ns
BCLK_IN HI Pulse Width t
BIH
2 ns
LRCLK_IN Setup t
LIS
To BCLK_IN rising 12 ns
LRCLK_IN Hold t
LIH
From BCLK_IN rising 0 ns
SDATA_INx Setup t
SIS
To BCLK_IN rising 3 ns
SDATA_INx Hold t
SIH
From BCLK_IN rising 2 ns
LRCLK_OUTx Setup t
LOS
Slave mode 2 ns
LRCLK_OUTx Hold t
LOH
Slave mode 2 ns
BCLK_OUTx Falling to LRCLK_OUTx
Timing Skew
t
TS
2 ns
SDATA_OUTx Delay
t
SODS
Slave mode, from
BCLK_OUTx falling
17 ns
SDATA_OUTx Delay
t
SODM
Master mode, from
BCLK_OUTx falling
17 ns
RESETB LO Pulse Width t
RLPW
10 ns
SPI PORT (AD1940)
CCLK Pulse Width LO t
CCPL
1 × INTMCLK (14)
2
ns
CCLK Pulse Width HI t
CCPH
1 × INTMCLK (14)
2
ns
CLATCH Setup t
CLS
To CCLK rising 0 ns
CLATCH Hold t
CLH
From CCLK rising 2 × INTMCLK + 4 (32)
2
ns
CLATCH Pulse Width HI t
CLPH
2 × INTMCLK (28)
2
ns
CDATA Setup t
CDS
To CCLK rising 0 ns
CDATA Hold t
CDH
From CCLK rising 2 × INTMCLK + 2 (30)
2
ns
COUT Delay t
COD
From CCLK rising 4 × INTMCLK +18 (74)
2
ns
I
2
C PORT (AD1941)
SCL Clock Frequency f
SCL
400 kHz
SCL Low t
SCLL
1.3 μs
SCL High t
SCLH
0.6 μs
Setup Time (Start Condition) t
SCS
Relevent for repeated start
condition
0.6 μs
Hold Time (Start Condition) t
SCH
First clock generated after
this period
0.6 μs
Setup Time (Stop Condition) t
SSH
0.6 μs
Data Setup Time t
DS
100 ns
SDA and SCL Rise Time t
SR
300 ns
SDA and SCL Fall Time t
SF
300 ns
Bus-Free Time t
BFT
Between stop and start 1.3 μs
1
All timing specifications are given for the default (I
2
S) states of the serial input control port and the serial output control ports. See Table 37.
2
These specifications are based on the internal master clock period in a specific application. In normal operation, the master clock runs at 1,536 × f
s
, so the internal
master clock at f
s
= 48 kHz has a 14 ns period. The values in parentheses are the timing values for f
s
= 48 kHz.