Datasheet

Data Sheet AD1938
Rev. E | Page 7 of 32
TIMING SPECIFICATIONS
−40°C < T
C
< +125°C, DVDD = 3.3 V ± 10%.
Table 7.
Parameter Condition Comments Min Max Unit
INPUT MASTER CLOCK (MCLK) AND RESET
t
MH
MCLK duty cycle DAC/ADC clock source = PLL clock @ 256 f
S
,
384 f
S
, 512 f
S
, and 768 f
S
40 60 %
t
MH
DAC/ADC clock source = direct MCLK @ 512 f
S
(bypass on-chip PLL)
40 60 %
f
MCLK
MCLK frequency PLL mode, 256 f
S
reference 6.9 13.8 MHz
f
MCLK
Direct 512 f
S
mode 27.6 MHz
t
PDR
RST
low 15 ns
t
PDRR
RST
recovery Reset to active output 4096 t
MCLK
PLL
Lock time MCLK and LR clock input 10 ms
256 f
S
VCO Clock, Output Duty Cycle,
MCLKO/XO Pin
40 60 %
SPI PORT See Figure 11
t
CCH
CCLK high 35 ns
t
CCL
CCLK low 35 ns
f
CCLK
CCLK frequency f
CCLK
= 1/t
CCP
, only t
CCP
shown in Figure 11 10 MHz
t
CDS
CIN setup To CCLK rising 10 ns
t
CDH
CIN hold From CCLK rising 10 ns
t
CLS
CLATCH
setup To CCLK rising 10 ns
t
CLH
CLATCH
hold From CCLK rising 10 ns
t
CLH
CLATCH
high
Not shown in Figure 11
10
ns
t
COE
COUT enable From CCLK falling 30 ns
t
COD
COUT delay From CCLK falling 30 ns
t
COH
COUT hold From CCLK falling, not shown in Figure 11 30 ns
t
COTS
COUT tristate From CCLK falling 30 ns
DAC SERIAL PORT See Figure 24
t
DBH
DBCLK high Slave mode 10 ns
t
DBL
DBCLK low Slave mode 10 ns
t
DLS
DLRCLK setup
To DBCLK rising, slave mode
10
ns
t
DLH
DLRCLK hold From DBCLK rising, slave mode 5 ns
t
DLS
DLRCLK skew From DBCLK falling, master mode −8 +8 ns
t
DDS
DSDATA setup To DBCLK rising 10 ns
t
DDH
DSDATA hold From DBCLK rising 5 ns
ADC SERIAL PORT See Figure 25
t
ABH
ABCLK high Slave mode 10 ns
t
ABL
ABCLK low Slave mode 10 ns
t
ALS
ALRCLK setup To ABCLK rising, slave mode 10 ns
t
ALH
ALRCLK hold From ABCLK rising, slave mode 5 ns
t
ALS
ALRCLK skew From ABCLK falling, master mode −8 +8 ns
t
ABDD
ASDATA delay From ABCLK falling 18 ns
AUXILIARY INTERFACE
t
AXDS
AAUXDATA setup To AUXBCLK rising 10 ns
t
AXDH
AAUXDATA hold From AUXBCLK rising 5 ns
t
DXDD
DAUXDATA delay From AUXBCLK falling 18 ns
t
XBH
AUXBCLK high 10 ns
t
XBL
AUXBCLK low
10
ns
t
DLS
AUXLRCLK setup To AUXBCLK rising 10 ns
t
DLH
AUXLRCLK hold From AUXBCLK rising 5 ns