Datasheet

AD1938 Data Sheet
Rev. E | Page 24 of 32
CONTROL REGISTERS
DEFINITIONS
The global address for the AD1938 is 0x04, shifted left one bit due to the R/
W
bit. All registers are reset to 0, except for the DAC volume
registers that are set to full volume.
Note that the first setting in each control register parameter is the default setting.
Table 14. Register Format
Global Address
R/
W
Register Address
Data
Bit
23:17 16 15:8 7:0
Table 15. Register Addresses and Functions
Address Function
0 PLL and Clock Control 0
1 PLL and Clock Control 1
2 DAC Control 0
3 DAC Control 1
4 DAC Control 2
5 DAC individual channel mutes
6 DAC L1 volume control
7 DAC R1 volume control
8 DAC L2 volume control
9 DAC R2 volume control
10 DAC L3 volume control
11
DAC R3 volume control
12 DAC L4 volume control
13 DAC R4 volume control
14 ADC Control 0
15 ADC Control 1
16
ADC Control 2
PLL AND CLOCK CONTROL REGISTERS
Table 16. PLL and Clock Control Register 0
Bit Value Function Description
0 0 Normal operation PLL power-down
1 Power-down
2:1 00 INPUT 256 (× 44.1 kHz or 48 kHz) MCLKI/XI pin functionality (PLL active), master clock rate setting
01 INPUT 384 (× 44.1 kHz or 48 kHz)
10
INPUT 512 (× 44.1 kHz or 48 kHz)
11 INPUT 768 (× 44.1 kHz or 48 kHz)
4:3 00 XTAL oscillator enabled MCLKO/XO pin, master clock rate setting
01 256 × f
S
VCO output
10 512 × f
S
VCO output
11 Off
6:5
00
MCLKI/XI
PLL input
01 DLRCLK
10 ALRCLK
11 Reserved
7 0 Disable: ADC and DAC idle Internal master clock enable
1 Enable: ADC and DAC active