Datasheet

AD1937
Rev. B | Page 9 of 36
TIMING DIAGRAMS
t
DBH
DBCLK
DLRCLK
DSDATAx
LEFT-JUSTIFIED
MODE
DSDATAx
RIGHT-JUSTIFIED
MODE
DSDATAx
I
2
S-JUSTIFIED
MODE
t
DLH
t
DBL
t
DLS
t
DDS
MSB
MSB
MSB LSB
MSB – 1
t
DDH
t
DDS
t
DDH
t
DDS
t
DDH
t
DDS
t
DDH
07414-025
RIGHT-JUSTIFIED
MODE
Figure 2. DAC Serial Timing
ABCLK
ALRCLK
ASDATAx
LEFT-JUSTIFIED
MODE
ASDATAx
ASDATAx
I
2
S-JUSTIFIED
MODE
t
ABH
LSB
MSB
MSB
MSB – 1
MSB
t
ABL
t
ALS
t
ABDD
t
ABDD
t
ABDD
t
ALH
0
7414-026
Figure 3. ADC Serial Timing