Datasheet

AD1937
Rev. B | Page 8 of 36
TIMING SPECIFICATIONS
−40°C < T
C
< +125°C, DVDD = 3.3 V ± 10%.
Table 8.
Parameter Condition Comments Min Max Unit
INPUT MASTER CLOCK (MCLK) AND RESET
t
MH
MCLK duty cycle
DAC/ADC clock source = PLL clock
@ 256 f
S
, 384 f
S
, 512 f
S
, and 768 f
S
40 60 %
t
MH
DAC/ADC clock source = direct MCLK
@ 512 f
S
(bypass on-chip PLL)
40 60 %
f
MCLK
MCLK frequency PLL mode, 256 f
S
reference 6.9 13.8 MHz
f
MCLK
Direct 512 f
S
mode 27.6 MHz
t
PDR
Low 15 ns
t
PDRR
Recovery Reset to active output 4096 t
MCLK
PLL
Lock Time MCLK or LRCLK 10 ms
256 f
S
VCO Clock, Output Duty Cycle,
MCLKO/MCLKXO Pin
40 60 %
I
2
C See Figure 13 and Figure 14
f
SCL
SCL clock frequency 400 kHz
t
SCLL
SCL low 1.3 μs
t
SCLH
SCL high 0.6 μs
t
SCS
Setup time (start condition) Relevent for repeated start condition 0.6 μs
t
SCH
Hold time (start condition) First clock generated after this period 0.6 μs
t
SSH
Setup time (stop condition) 0.6 μs
t
DS
Data setup time 100 ns
t
SR
SDA and SCL rise time 300 ns
t
SF
SDA and SCL fall time 300 ns
t
BFT
Bus-free time Between stop and start 1.3 μs
DAC SERIAL PORT See Figure 2
t
DBH
DBCLK high Slave mode 10 ns
t
DBL
DBCLK low Slave mode 10 ns
t
DLS
DLRCLK setup To DBCLK rising, slave mode 10 ns
DLRCLK skew From DBCLK falling, master mode −8 +8 ns
t
DLH
DLRCLK hold From DBCLK rising, slave mode 5 ns
t
DDS
DSDATA setup To DBCLK rising 10 ns
t
DDH
DSDATA hold From DBCLK rising 5 ns
ADC SERIAL PORT See Figure 3
t
ABH
ABCLK high Slave mode 10 ns
t
ABL
ABCLK low Slave mode 10 ns
t
ALS
ALRCLK setup To ABCLK rising, slave mode 10 ns
ALRCLK skew From ABCLK falling, master mode −8 +8 ns
t
ALH
ALRCLK hold From ABCLK rising, slave mode 5 ns
t
ABDD
ASDATA delay From ABCLK falling, any mode 18 ns
AUXILIARY INTERFACE
t
AXDS
AAUXDATA setup To AUXBCLK rising 10 ns
t
AXDH
AAUXDATA hold From AUXBCLK rising 5 ns
t
DXDD
DAUXDATA delay From AUXBCLK falling 18 ns
t
XBH
AUXBCLK high 10 ns
t
XBL
AUXBCLK low 10 ns
t
DLS
AUXLRCLK setup To AUXBCLK rising 10 ns
t
DLH
AUXLRCLK hold From AUXBCLK rising 5 ns