Datasheet

AD1937
Rev. B | Page 31 of 36
Table 31. ADC Control 2 Register (Address 16, 0x10)
Bit Value Function Description
0 0 50/50 (allows 32, 24, 20, or 16 BCLKs per channel) ALRCLK format
1 Pulse (32 BCLKs per channel)
1 0 Drive out on falling edge (DEF) ABCLK polarity
1 Drive out on rising edge
2 0 Left low ALRCLK polarity
1 Left high
3 0 Slave ALRCLK master/slave
1 Master
5:4 00 64 cycles ABCLKs per frame
01 128 cycles
10 256 cycles
11 512 cycles
6 0 Slave ABCLK master/slave
1 Master
7 0 ABCLK pin ABCLK source
1 Internally generated